From: Alexandre Courbot <acourbot@nvidia.com>
To: David Airlie <airlied@linux.ie>, Ben Skeggs <bskeggs@redhat.com>,
Lucas Stach <dev@lynxeye.de>,
Thierry Reding <thierry.reding@gmail.com>
Cc: <nouveau@lists.freedesktop.org>,
<dri-devel@lists.freedesktop.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <gnurou@gmail.com>,
Alexandre Courbot <acourbot@nvidia.com>
Subject: [PATCH 2/4] drm/ttm: introduce dma cache sync helpers
Date: Mon, 19 May 2014 16:10:56 +0900 [thread overview]
Message-ID: <1400483458-9648-3-git-send-email-acourbot@nvidia.com> (raw)
In-Reply-To: <1400483458-9648-1-git-send-email-acourbot@nvidia.com>
From: Lucas Stach <dev@lynxeye.de>
On arches with non-coherent PCI, we need to flush caches ourselfes at
the appropriate places. Introduce two small helpers to make things easy
for TTM based drivers.
Signed-off-by: Lucas Stach <dev@lynxeye.de>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/drm/ttm/ttm_tt.c | 25 +++++++++++++++++++++++++
include/drm/ttm/ttm_bo_driver.h | 28 ++++++++++++++++++++++++++++
2 files changed, 53 insertions(+)
diff --git a/drivers/gpu/drm/ttm/ttm_tt.c b/drivers/gpu/drm/ttm/ttm_tt.c
index 75f319090043..05a316b71ad1 100644
--- a/drivers/gpu/drm/ttm/ttm_tt.c
+++ b/drivers/gpu/drm/ttm/ttm_tt.c
@@ -38,6 +38,7 @@
#include <linux/swap.h>
#include <linux/slab.h>
#include <linux/export.h>
+#include <linux/dma-mapping.h>
#include <drm/drm_cache.h>
#include <drm/drm_mem_util.h>
#include <drm/ttm/ttm_module.h>
@@ -248,6 +249,30 @@ void ttm_dma_tt_fini(struct ttm_dma_tt *ttm_dma)
}
EXPORT_SYMBOL(ttm_dma_tt_fini);
+void ttm_dma_tt_cache_sync_for_device(struct ttm_dma_tt *ttm_dma,
+ struct device *dev)
+{
+ int i;
+
+ for (i = 0; i < ttm_dma->ttm.num_pages; i++) {
+ dma_sync_single_for_device(dev, ttm_dma->dma_address[i],
+ PAGE_SIZE, DMA_TO_DEVICE);
+ }
+}
+EXPORT_SYMBOL(ttm_dma_tt_cache_sync_for_device);
+
+void ttm_dma_tt_cache_sync_for_cpu(struct ttm_dma_tt *ttm_dma,
+ struct device *dev)
+{
+ int i;
+
+ for (i = 0; i < ttm_dma->ttm.num_pages; i++) {
+ dma_sync_single_for_cpu(dev, ttm_dma->dma_address[i],
+ PAGE_SIZE, DMA_FROM_DEVICE);
+ }
+}
+EXPORT_SYMBOL(ttm_dma_tt_cache_sync_for_cpu);
+
void ttm_tt_unbind(struct ttm_tt *ttm)
{
int ret;
diff --git a/include/drm/ttm/ttm_bo_driver.h b/include/drm/ttm/ttm_bo_driver.h
index a5183da3ef92..52fb709568fc 100644
--- a/include/drm/ttm/ttm_bo_driver.h
+++ b/include/drm/ttm/ttm_bo_driver.h
@@ -41,6 +41,7 @@
#include <linux/fs.h>
#include <linux/spinlock.h>
#include <linux/reservation.h>
+#include <linux/device.h>
struct ttm_backend_func {
/**
@@ -690,6 +691,33 @@ extern int ttm_tt_swapout(struct ttm_tt *ttm,
*/
extern void ttm_tt_unpopulate(struct ttm_tt *ttm);
+/**
+ * ttm_dma_tt_cache_sync_for_device:
+ *
+ * @ttm A struct ttm_tt of the type returned by ttm_dma_tt_init.
+ * @dev A struct device representing the device to which to sync.
+ *
+ * This function will flush the CPU caches on arches where snooping in the
+ * TT is not available. On fully coherent arches this will turn into an (almost)
+ * noop. This makes sure that data written by the CPU is visible to the device.
+ */
+extern void ttm_dma_tt_cache_sync_for_device(struct ttm_dma_tt *ttm_dma,
+ struct device *dev);
+
+/**
+ * ttm_dma_tt_cache_sync_for_cpu:
+ *
+ * @ttm A struct ttm_tt of the type returned by ttm_dma_tt_init.
+ * @dev A struct device representing the device from which to sync.
+ *
+ * This function will invalidate the CPU caches on arches where snooping in the
+ * TT is not available. On fully coherent arches this will turn into an (almost)
+ * noop. This makes sure that the CPU does not read any stale cached or
+ * prefetched data.
+ */
+extern void ttm_dma_tt_cache_sync_for_cpu(struct ttm_dma_tt *ttm_dma,
+ struct device *dev);
+
/*
* ttm_bo.c
*/
--
1.9.2
next prev parent reply other threads:[~2014-05-19 7:12 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-05-19 7:10 [PATCH 0/4] drm/ttm: nouveau: memory coherency fixes for ARM Alexandre Courbot
2014-05-19 7:10 ` [PATCH 1/4] drm/ttm: recognize ARM arch in ioprot handler Alexandre Courbot
2014-05-19 7:10 ` Alexandre Courbot [this message]
2014-05-19 8:33 ` [PATCH 2/4] drm/ttm: introduce dma cache sync helpers Thierry Reding
2014-05-23 5:49 ` Alexandre Courbot
2014-05-23 7:31 ` Thierry Reding
2014-05-19 7:10 ` [PATCH 3/4] drm/nouveau: hook up cache sync functions Alexandre Courbot
2014-05-19 8:46 ` Thierry Reding
2014-05-19 9:44 ` Lucas Stach
2014-05-23 6:00 ` Alexandre Courbot
2014-05-19 9:31 ` Lucas Stach
2014-05-23 6:01 ` Alexandre Courbot
2014-05-19 7:10 ` [PATCH 4/4] drm/nouveau: introduce CPU cache flushing macro Alexandre Courbot
2014-05-19 9:02 ` Thierry Reding
2014-05-19 9:22 ` Lucas Stach
2014-05-19 10:03 ` Thierry Reding
2014-05-19 10:27 ` [Nouveau] " Daniel Vetter
2014-05-23 6:58 ` Alexandre Courbot
2014-06-09 10:41 ` Alexandre Courbot
2014-06-12 13:50 ` Alexandre Courbot
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