* [PATCH v2 2/4] mfd: intel_soc_pmic: I2C interface
2014-05-22 6:38 [PATCH v2 0/4] mfd: Intel SoC Power Management IC Zhu, Lejun
@ 2014-05-22 6:38 ` Zhu, Lejun
2014-05-22 6:38 ` [PATCH v2 3/4] mfd: intel_soc_pmic: Crystal Cove support Zhu, Lejun
2014-05-22 6:38 ` [PATCH v2 4/4] mfd: intel_soc_pmic: Build files Zhu, Lejun
2 siblings, 0 replies; 4+ messages in thread
From: Zhu, Lejun @ 2014-05-22 6:38 UTC (permalink / raw)
To: lee.jones, sameo; +Cc: linux-kernel, jacob.jun.pan, bin.yang, lejun.zhu
The Intel SoC PMIC devices are connected to the CPU via the I2C
interface. This patch provides support of the related I2C operations.
v2:
- Use regmap instead of creating our own I2C read/write callbacks.
Signed-off-by: Yang, Bin <bin.yang@intel.com>
Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com>
---
drivers/mfd/intel_soc_pmic_i2c.c | 148 +++++++++++++++++++++++++++++++++++++++
1 file changed, 148 insertions(+)
create mode 100644 drivers/mfd/intel_soc_pmic_i2c.c
diff --git a/drivers/mfd/intel_soc_pmic_i2c.c b/drivers/mfd/intel_soc_pmic_i2c.c
new file mode 100644
index 0000000..b6b8ee1
--- /dev/null
+++ b/drivers/mfd/intel_soc_pmic_i2c.c
@@ -0,0 +1,148 @@
+/*
+ * intel_soc_pmic_i2c.c - Intel SoC PMIC MFD Driver
+ *
+ * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Author: Yang, Bin <bin.yang@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/mfd/core.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <linux/acpi.h>
+#include <linux/version.h>
+#include <linux/gpio/consumer.h>
+#include <linux/regmap.h>
+#include <linux/mfd/intel_soc_pmic.h>
+#include "intel_soc_pmic_core.h"
+
+static struct i2c_client *pmic_i2c_client;
+static struct intel_soc_pmic *pmic_i2c;
+
+static void pmic_shutdown(struct i2c_client *client)
+{
+ disable_irq(pmic_i2c_client->irq);
+ return;
+}
+
+static int pmic_suspend(struct device *dev)
+{
+ disable_irq(pmic_i2c_client->irq);
+ return 0;
+}
+
+static int pmic_resume(struct device *dev)
+{
+ enable_irq(pmic_i2c_client->irq);
+ return 0;
+}
+
+static const struct dev_pm_ops pmic_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(pmic_suspend, pmic_resume)
+};
+
+static int pmic_i2c_lookup_gpio(struct device *dev, int acpi_index)
+{
+ struct gpio_desc *desc;
+ int gpio;
+
+ desc = gpiod_get_index(dev, KBUILD_MODNAME, acpi_index);
+ if (IS_ERR(desc))
+ return PTR_ERR(desc);
+
+ gpio = desc_to_gpio(desc);
+
+ gpiod_put(desc);
+
+ return gpio;
+}
+
+static int pmic_i2c_probe(struct i2c_client *i2c,
+ const struct i2c_device_id *id)
+{
+ if (pmic_i2c_client != NULL || pmic_i2c != NULL)
+ return -EBUSY;
+
+ pmic_i2c = (struct intel_soc_pmic *)id->driver_data;
+ pmic_i2c_client = i2c;
+ pmic_i2c->dev = &i2c->dev;
+ pmic_i2c->irq = i2c->irq;
+ pmic_i2c->pmic_int_gpio = pmic_i2c_lookup_gpio(pmic_i2c->dev, 0);
+ pmic_i2c->regmap = devm_regmap_init_i2c(i2c, pmic_i2c->regmap_cfg);
+
+ return intel_pmic_add(pmic_i2c);
+}
+
+static int pmic_i2c_remove(struct i2c_client *i2c)
+{
+ int ret = intel_pmic_remove(pmic_i2c);
+
+ pmic_i2c_client = NULL;
+ pmic_i2c = NULL;
+
+ return ret;
+}
+
+static const struct i2c_device_id pmic_i2c_id[] = {
+ { "crystal_cove", (kernel_ulong_t)&crystal_cove_pmic},
+ { "INT33FD", (kernel_ulong_t)&crystal_cove_pmic},
+ { "INT33FD:00", (kernel_ulong_t)&crystal_cove_pmic},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, pmic_i2c_id);
+
+static struct acpi_device_id pmic_acpi_match[] = {
+ { "INT33FD", (kernel_ulong_t)&crystal_cove_pmic},
+ { },
+};
+MODULE_DEVICE_TABLE(acpi, pmic_acpi_match);
+
+static struct i2c_driver pmic_i2c_driver = {
+ .driver = {
+ .name = "intel_soc_pmic_i2c",
+ .owner = THIS_MODULE,
+ .pm = &pmic_pm_ops,
+ .acpi_match_table = ACPI_PTR(pmic_acpi_match),
+ },
+ .probe = pmic_i2c_probe,
+ .remove = pmic_i2c_remove,
+ .id_table = pmic_i2c_id,
+ .shutdown = pmic_shutdown,
+};
+
+static int __init pmic_i2c_init(void)
+{
+ int ret;
+
+ ret = i2c_add_driver(&pmic_i2c_driver);
+ if (ret != 0)
+ pr_err("Failed to register pmic I2C driver: %d\n", ret);
+
+ return ret;
+}
+subsys_initcall(pmic_i2c_init);
+
+static void __exit pmic_i2c_exit(void)
+{
+ i2c_del_driver(&pmic_i2c_driver);
+}
+module_exit(pmic_i2c_exit);
+
+MODULE_DESCRIPTION("I2C driver for Intel SoC PMIC");
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Yang, Bin <bin.yang@intel.com>");
--
1.8.3.2
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2 3/4] mfd: intel_soc_pmic: Crystal Cove support
2014-05-22 6:38 [PATCH v2 0/4] mfd: Intel SoC Power Management IC Zhu, Lejun
2014-05-22 6:38 ` [PATCH v2 2/4] mfd: intel_soc_pmic: I2C interface Zhu, Lejun
@ 2014-05-22 6:38 ` Zhu, Lejun
2014-05-22 6:38 ` [PATCH v2 4/4] mfd: intel_soc_pmic: Build files Zhu, Lejun
2 siblings, 0 replies; 4+ messages in thread
From: Zhu, Lejun @ 2014-05-22 6:38 UTC (permalink / raw)
To: lee.jones, sameo; +Cc: linux-kernel, jacob.jun.pan, bin.yang, lejun.zhu
Crystal Cove is the PMIC in Baytrail-T platform. This patch provides
chip-specific support for Crystal Cove.
v2:
- Add regmap_config for Crystal Cove.
Signed-off-by: Yang, Bin <bin.yang@intel.com>
Signed-off-by: Zhu, Lejun <lejun.zhu@linux.intel.com>
---
drivers/mfd/intel_soc_pmic_crc.c | 165 +++++++++++++++++++++++++++++++++++++++
1 file changed, 165 insertions(+)
create mode 100644 drivers/mfd/intel_soc_pmic_crc.c
diff --git a/drivers/mfd/intel_soc_pmic_crc.c b/drivers/mfd/intel_soc_pmic_crc.c
new file mode 100644
index 0000000..6ab4cbf
--- /dev/null
+++ b/drivers/mfd/intel_soc_pmic_crc.c
@@ -0,0 +1,165 @@
+/*
+ * intel_soc_pmic_crc.c - Device access for Crystal Cove PMIC
+ *
+ * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version
+ * 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Author: Yang, Bin <bin.yang@intel.com>
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/mfd/core.h>
+#include <linux/err.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+#include <linux/interrupt.h>
+#include <linux/acpi.h>
+#include <linux/version.h>
+#include <linux/regmap.h>
+#include <linux/mfd/intel_soc_pmic.h>
+#include "intel_soc_pmic_core.h"
+
+#define CRYSTAL_COVE_IRQ_NUM 7
+#define CRYSTAL_COVE_MAX_REGISTER 0xBD
+
+#define CHIPID 0x00
+#define CHIPVER 0x01
+#define IRQLVL1 0x02
+#define MIRQLVL1 0x0E
+enum {
+ PWRSRC_IRQ = 0,
+ THRM_IRQ,
+ BCU_IRQ,
+ ADC_IRQ,
+ CHGR_IRQ,
+ GPIO_IRQ,
+ VHDMIOCP_IRQ
+};
+
+static struct resource gpio_resources[] = {
+ {
+ .name = "GPIO",
+ .start = GPIO_IRQ,
+ .end = GPIO_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource pwrsrc_resources[] = {
+ {
+ .name = "PWRSRC",
+ .start = PWRSRC_IRQ,
+ .end = PWRSRC_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource adc_resources[] = {
+ {
+ .name = "ADC",
+ .start = ADC_IRQ,
+ .end = ADC_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct resource thermal_resources[] = {
+ {
+ .name = "THERMAL",
+ .start = THRM_IRQ,
+ .end = THRM_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct resource bcu_resources[] = {
+ {
+ .name = "BCU",
+ .start = BCU_IRQ,
+ .end = BCU_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+static struct mfd_cell crystal_cove_dev[] = {
+ {
+ .name = "crystal_cove_pwrsrc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(pwrsrc_resources),
+ .resources = pwrsrc_resources,
+ },
+ {
+ .name = "crystal_cove_adc",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(adc_resources),
+ .resources = adc_resources,
+ },
+ {
+ .name = "crystal_cove_thermal",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(thermal_resources),
+ .resources = thermal_resources,
+ },
+ {
+ .name = "crystal_cove_bcu",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(bcu_resources),
+ .resources = bcu_resources,
+ },
+ {
+ .name = "crystal_cove_gpio",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(gpio_resources),
+ .resources = gpio_resources,
+ },
+ {NULL, },
+};
+
+#define CRC_IRQREGMAP_VALUE(irq) { \
+ {MIRQLVL1, irq, 1, 0}, \
+ {IRQLVL1, irq, 1, 0}, \
+ INTEL_PMIC_REG_NULL, \
+ }
+
+static struct intel_pmic_irqregmap crystal_cove_irqregmap[] = {
+ [PWRSRC_IRQ] = CRC_IRQREGMAP_VALUE(PWRSRC_IRQ),
+ [THRM_IRQ] = CRC_IRQREGMAP_VALUE(THRM_IRQ),
+ [BCU_IRQ] = CRC_IRQREGMAP_VALUE(BCU_IRQ),
+ [ADC_IRQ] = CRC_IRQREGMAP_VALUE(ADC_IRQ),
+ [CHGR_IRQ] = CRC_IRQREGMAP_VALUE(CHGR_IRQ),
+ [GPIO_IRQ] = CRC_IRQREGMAP_VALUE(GPIO_IRQ),
+ [VHDMIOCP_IRQ] = CRC_IRQREGMAP_VALUE(VHDMIOCP_IRQ),
+};
+
+static struct regmap_config crystal_cove_regmap_config = {
+ .reg_bits = 8,
+ .val_bits = 8,
+
+ .max_register = CRYSTAL_COVE_MAX_REGISTER,
+ .cache_type = REGCACHE_NONE,
+};
+
+static int crystal_cove_init(void)
+{
+ pr_debug("Crystal Cove: ID 0x%02X, VERSION 0x%02X\n",
+ intel_soc_pmic_readb(CHIPID), intel_soc_pmic_readb(CHIPVER));
+ return 0;
+}
+
+struct intel_soc_pmic crystal_cove_pmic = {
+ .label = "crystal cove",
+ .irq_flags = IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+ .init = crystal_cove_init,
+ .cell_dev = crystal_cove_dev,
+ .irq_regmap = crystal_cove_irqregmap,
+ .irq_num = CRYSTAL_COVE_IRQ_NUM,
+ .regmap_cfg = &crystal_cove_regmap_config,
+};
--
1.8.3.2
^ permalink raw reply [flat|nested] 4+ messages in thread