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From: Marc Zyngier <marc.zyngier@arm.com>
To: linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Jiang Liu <jiang.liu@linux.intel.com>,
	Thomas Gleixner <tglx@linutronix.de>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	Yingjoe Chen <yingjoe.chen@mediatek.com>,
	Will Deacon <will.deacon@arm.com>,
	Catalin marinas <catalin.marinas@arm.com>,
	Mark Rutland <mark.rutland@arm.com>
Subject: [PATCH 15/15] irqchip: GICv3: Binding updates for ITS
Date: Tue, 11 Nov 2014 15:48:13 +0000	[thread overview]
Message-ID: <1415720893-13371-16-git-send-email-marc.zyngier@arm.com> (raw)
In-Reply-To: <1415720893-13371-1-git-send-email-marc.zyngier@arm.com>

Add the documentation for the bindings describing the GICv3 ITS.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
---
 Documentation/devicetree/bindings/arm/gic-v3.txt | 39 ++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/gic-v3.txt b/Documentation/devicetree/bindings/arm/gic-v3.txt
index 33cd05e..ddfade4 100644
--- a/Documentation/devicetree/bindings/arm/gic-v3.txt
+++ b/Documentation/devicetree/bindings/arm/gic-v3.txt
@@ -49,11 +49,29 @@ Optional
   occupied by the redistributors. Required if more than one such
   region is present.
 
+Sub-nodes:
+
+GICv3 has one or more Interrupt Translation Services (ITS) that are
+used to route Message Signalled Interrupts (MSI) to the CPUs.
+
+These nodes must have the following properties:
+- compatible : Should at least contain  "arm,gic-v3-its".
+- msi-controller : Boolean property. Identifies the node as an MSI controller
+- reg: Specifies the base physical address and size of the ITS
+  registers.
+
+The main GIC node must contain the appropriate #address-cells,
+#size-cells and ranges properties for the reg property of all ITS
+nodes.
+
 Examples:
 
 	gic: interrupt-controller@2cf00000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
 		interrupt-controller;
 		reg = <0x0 0x2f000000 0 0x10000>,	// GICD
 		      <0x0 0x2f100000 0 0x200000>,	// GICR
@@ -61,11 +79,20 @@ Examples:
 		      <0x0 0x2c010000 0 0x2000>,	// GICH
 		      <0x0 0x2c020000 0 0x2000>;	// GICV
 		interrupts = <1 9 4>;
+
+		gic-its@2c200000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2c200000 0 0x200000>;
+		};
 	};
 
 	gic: interrupt-controller@2c010000 {
 		compatible = "arm,gic-v3";
 		#interrupt-cells = <3>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
 		interrupt-controller;
 		redistributor-stride = <0x0 0x40000>;	// 256kB stride
 		#redistributor-regions = <2>;
@@ -76,4 +103,16 @@ Examples:
 		      <0x0 0x2c060000 0 0x2000>,	// GICH
 		      <0x0 0x2c080000 0 0x2000>;	// GICV
 		interrupts = <1 9 4>;
+
+		gic-its@2c200000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2c200000 0 0x200000>;
+		};
+
+		gic-its@2c400000 {
+			compatible = "arm,gic-v3-its";
+			msi-controller;
+			reg = <0x0 0x2c400000 0 0x200000>;
+		};
 	};
-- 
2.0.4


  parent reply	other threads:[~2014-11-11 15:48 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-11-11 15:47 [PATCH 00/15] arm64: PCI/MSI: GICv3 ITS support (stacked domain edition) Marc Zyngier
2014-11-11 15:47 ` [PATCH 01/15] genirq: Add a few more helper funtions to support stacked irq_chip Marc Zyngier
2014-11-11 15:48 ` [PATCH 02/15] PCI/MSI: genirq: allow architecture-specific override of flow handler Marc Zyngier
2014-11-11 15:48 ` [PATCH 03/15] arm64: MSI: Add support for stacked MSI domain Marc Zyngier
2014-11-11 15:48 ` [PATCH 04/15] irqchip: GICv3: Convert to domain hierarchy Marc Zyngier
2014-11-11 15:48 ` [PATCH 05/15] irqchip: GICv3: rework redistributor structure Marc Zyngier
2014-11-11 15:48 ` [PATCH 06/15] irqchip: GICv3: ITS command queue Marc Zyngier
2014-11-11 15:48 ` [PATCH 07/15] irqchip: GICv3: ITS: irqchip implementation Marc Zyngier
2014-11-11 15:48 ` [PATCH 08/15] irqchip: GICv3: ITS: LPI allocator Marc Zyngier
2014-11-11 15:48 ` [PATCH 09/15] irqchip: GICv3: ITS: tables allocators Marc Zyngier
2014-11-11 15:48 ` [PATCH 10/15] irqchip: GICv3: ITS: device allocation and configuration Marc Zyngier
2014-11-11 15:48 ` [PATCH 11/15] irqchip: GICv3: ITS: MSI support Marc Zyngier
2014-11-11 15:48 ` [PATCH 12/15] irqchip: GICv3: ITS: DT probing and initialization Marc Zyngier
2014-11-11 15:48 ` [PATCH 13/15] irqchip: GICv3: ITS: plug ITS init into main GICv3 code Marc Zyngier
2014-11-11 15:48 ` [PATCH 14/15] irqchip: GICv3: ITS: enable compilation of the ITS driver Marc Zyngier
2014-11-11 15:48 ` Marc Zyngier [this message]
2014-11-11 16:10 ` [PATCH 00/15] arm64: PCI/MSI: GICv3 ITS support (stacked domain edition) Jiang Liu
2014-11-11 16:27   ` Marc Zyngier
2014-11-11 16:32     ` Jiang Liu
2014-11-11 18:32       ` Marc Zyngier

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