From: Rhyland Klein <rklein@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>,
Stephen Warren <swarren@wwwdotorg.org>,
Stephen Boyd <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>,
Alexandre Courbot <gnurou@gmail.com>,
linux-clk@vger.kernel.org, linux-tegra@vger.kernel.org,
linux-kernel@vger.kernel.org, Rhyland Klein <rklein@nvidia.com>,
Bill Huang <bilhuang@nvidia.com>
Subject: [PATCH v2 14/19] clk: tegra: pll: Adjust vco_min if SDM present
Date: Wed, 29 Apr 2015 13:21:44 -0400 [thread overview]
Message-ID: <1430328109-537-15-git-send-email-rklein@nvidia.com> (raw)
In-Reply-To: <1430328109-537-1-git-send-email-rklein@nvidia.com>
From: Bill Huang <bilhuang@nvidia.com>
This code makes use of the SDM fractional divider if present to
contrain the allowable programming range of the PLL divider register
bitfields to take advantage of higher frequency granularity that can
be induced by the SDM divider.
Based on original work by Aleksandr Frid <afrid@nvidia.com>
Signed-off-by: Bill Huang <bilhuang@nvidia.com>
---
drivers/clk/tegra/clk-pll.c | 29 ++++++++++++++++++++++++++++-
drivers/clk/tegra/clk.h | 2 ++
2 files changed, 30 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c
index edc388f02a66..00f0e621533a 100644
--- a/drivers/clk/tegra/clk-pll.c
+++ b/drivers/clk/tegra/clk-pll.c
@@ -1635,7 +1635,6 @@ static const struct clk_ops tegra_clk_plle_tegra114_ops = {
.recalc_rate = clk_pll_recalc_rate,
};
-
struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
void __iomem *clk_base, void __iomem *pmc,
unsigned long flags,
@@ -1662,6 +1661,10 @@ struct clk *tegra_clk_register_pllxc(const char *name, const char *parent_name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
err = _setup_dynamic_ramp(pll_params, clk_base, parent_rate);
if (err)
return ERR_PTR(err);
@@ -1700,6 +1703,10 @@ struct clk *tegra_clk_register_pllre(const char *name, const char *parent_name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
@@ -1756,6 +1763,10 @@ struct clk *tegra_clk_register_pllm(const char *name, const char *parent_name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll_params->flags |= TEGRA_PLLM;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
@@ -2186,6 +2197,10 @@ struct clk *tegra_clk_register_pllc_tegra210(const char *name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
@@ -2224,6 +2239,10 @@ struct clk *tegra_clk_register_pllxc_tegra210(const char *name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
if (IS_ERR(pll))
return ERR_CAST(pll);
@@ -2271,6 +2290,10 @@ struct clk *tegra_clk_register_pllss_tegra210(const char *name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
/* initialize PLL to minimum rate */
cfg.m = _pll_fixed_mdiv(pll_params, parent_rate);
@@ -2335,6 +2358,10 @@ struct clk *tegra_clk_register_pllmb(const char *name, const char *parent_name,
pll_params->vco_min = _clip_vco_min(pll_params->vco_min, parent_rate);
+ if (pll_params->adjust_vco)
+ pll_params->vco_min = pll_params->adjust_vco(pll_params,
+ parent_rate);
+
pll_params->flags |= TEGRA_PLL_BYPASS;
pll_params->flags |= TEGRA_PLLMB;
pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);
diff --git a/drivers/clk/tegra/clk.h b/drivers/clk/tegra/clk.h
index 9e37defb063f..27075a586e79 100644
--- a/drivers/clk/tegra/clk.h
+++ b/drivers/clk/tegra/clk.h
@@ -248,6 +248,8 @@ struct tegra_clk_pll_params {
int (*calc_rate)(struct clk_hw *hw,
struct tegra_clk_pll_freq_table *cfg,
unsigned long rate, unsigned long parent_rate);
+ unsigned long (*adjust_vco)(struct tegra_clk_pll_params *pll_params,
+ unsigned long parent_rate);
};
#define TEGRA_PLL_USE_LOCK BIT(0)
--
1.7.9.5
next prev parent reply other threads:[~2015-04-29 17:23 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-04-29 17:21 [PATCH v2 00/19] Tegra210 Clock Support Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 01/19] clk: tegra: Modify tegra_audio_clk_init to accept more plls Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 02/19] clk: tegra: periph: add new periph clks and muxes for Tegra210 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 03/19] clk: tegra: pll: add tegra_pll_wait_for_lock to clk header Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 04/19] clk: tegra: pll: simplify clk_enable_path Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 05/19] clk: tegra: pll: update warning msg Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 06/19] clk: tegra: pll-params: change misc_reg count from 3 -> 6 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 07/19] clk: tegra: pll: Don't unconditionally set LOCK flags Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 08/19] clk: tegra: pll: Add logic for handling SDM data Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 09/19] clk: tegra: pll: Add logic for SS Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 10/19] clk: tegra: pll: Add logic for out-of-table rates for T210 Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 11/19] clk: tegra: pll: Add code to handle if resets are supported by PLL Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 12/19] clk: tegra: pll: Add specialized logic for T210 Rhyland Klein
2015-04-29 18:27 ` Andrew Bresticker
2015-04-29 21:42 ` Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 13/19] clk: tegra: pll: Add support for PLLMB " Rhyland Klein
2015-04-30 10:11 ` Peter De Schrijver
2015-04-29 17:21 ` Rhyland Klein [this message]
2015-04-29 17:21 ` [PATCH v2 15/19] clk: tegra: pll: Add dyn_ramp callback Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 16/19] clk: tegra: pll: Add Set_default logic Rhyland Klein
2015-04-30 10:12 ` Peter De Schrijver
2015-04-30 15:31 ` Rhyland Klein
2015-05-11 11:50 ` Peter De Schrijver
2015-05-11 15:07 ` Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 17/19] clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 18/19] clk: tegra: Add Super Gen5 Logic Rhyland Klein
2015-04-29 17:21 ` [PATCH v2 19/19] clk: tegra210: add support for Tegra210 clocks Rhyland Klein
2015-04-30 20:43 ` Andrew Bresticker
2015-04-30 20:57 ` Rhyland Klein
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