[PATCH 0/3] ARM: socfpga: enable SMP for Arria10

[PATCH 0/3] ARM: socfpga: enable SMP for Arria10

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Hi,

The goal of these 3 patches is to enable SMP on the Arria10 platform. During
the process, I found it would be much cleaner to convert the Cyclone5/Arria5
platform to use CPU_METHOD_OF_DECLARE instead of the machine descriptor.

The procedure to enable SMP on the Arria10 platform is similar to the Cyclone5/
Arria5 with the exception of a few differences in the register offset of the
reset manager designed to bring the secondary core out of reset. So instead of
littering the code with machine lookups, just use CPU_METHOD_OF_DECLARE.

Thanks,

Dinh Nguyen (3):
  ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5
  ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10
  ARM: socfpga: dts: add enable-method property for cpu nodes

 arch/arm/boot/dts/socfpga.dtsi         |  1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi |  1 +
 arch/arm/mach-socfpga/core.h           |  2 ++
 arch/arm/mach-socfpga/platsmp.c        | 32 ++++++++++++++++++++++++++++++++
 arch/arm/mach-socfpga/socfpga.c        |  1 -
 5 files changed, 36 insertions(+), 1 deletion(-)

-- 
2.2.1

[PATCH 1/3] ARM: socfpga: use CPU_METHOD_OF_DECLARE for socfpga_cyclone5

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Convert cyclone5/arria5 to use CPU_METHOD_OF_DECLARE for smp operations.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/platsmp.c | 2 ++
 arch/arm/mach-socfpga/socfpga.c | 1 -
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 7886eae..08250c8 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -90,3 +90,5 @@ struct smp_operations socfpga_smp_ops __initdata = {
 	.cpu_die		= socfpga_cpu_die,
 #endif
 };
+
+CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index b63dec6..a154920 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -78,7 +78,6 @@ static const char *altera_dt_match[] = {
 DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
 	.l2c_aux_val	= 0,
 	.l2c_aux_mask	= ~0,
-	.smp		= smp_ops(socfpga_smp_ops),
 	.init_irq	= socfpga_init_irq,
 	.restart	= socfpga_cyclone5_restart,
 	.dt_compat	= altera_dt_match,
-- 
2.2.1

[PATCH 2/3] ARM: socfpga: add CPU_METHOD_OF_DECLARE for Arria 10

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add boot_secondary implementation for the Arria10 platform. Bringing up
the secondary core on the Arria 10 platform is pretty similar to the
Cyclone/Arria 5 platform, with the exception of the following differences:

- Register offset to bringup CPU1 out of reset is different.
- The cpu1-start-addr for Arria10 contains an additional nibble.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/mach-socfpga/core.h    |  2 ++
 arch/arm/mach-socfpga/platsmp.c | 30 ++++++++++++++++++++++++++++++
 2 files changed, 32 insertions(+)

diff --git a/arch/arm/mach-socfpga/core.h b/arch/arm/mach-socfpga/core.h
index 5913bbb..7637b7f 100644
--- a/arch/arm/mach-socfpga/core.h
+++ b/arch/arm/mach-socfpga/core.h
@@ -25,6 +25,8 @@
 #define SOCFPGA_RSTMGR_MODPERRST	0x14
 #define SOCFPGA_RSTMGR_BRGMODRST	0x1c
 
+#define SOCFPGA_A10_RSTMGR_MODMPURST	0x20
+
 /* System Manager bits */
 #define RSTMGR_CTRL_SWCOLDRSTREQ	0x1	/* Cold Reset */
 #define RSTMGR_CTRL_SWWARMRSTREQ	0x2	/* Warm Reset */
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 08250c8..bcc7ce8 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -54,6 +54,27 @@ static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 	return 0;
 }
 
+static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
+
+	if (socfpga_cpu1start_addr) {
+		memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
+
+		writel(virt_to_phys(socfpga_secondary_startup),
+		       sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
+
+		flush_cache_all();
+		smp_wmb();
+		outer_clean_range(0, trampoline_size);
+
+		/* This will release CPU #1 out of reset. */
+		writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
+	}
+
+	return 0;
+}
+
 static void __init socfpga_smp_prepare_cpus(unsigned int max_cpus)
 {
 	struct device_node *np;
@@ -91,4 +112,13 @@ struct smp_operations socfpga_smp_ops __initdata = {
 #endif
 };
 
+struct smp_operations socfpga_a10_smp_ops __initdata = {
+	.smp_prepare_cpus	= socfpga_smp_prepare_cpus,
+	.smp_boot_secondary	= socfpga_a10_boot_secondary,
+#ifdef CONFIG_HOTPLUG_CPU
+	.cpu_die		= socfpga_cpu_die,
+#endif
+};
+
 CPU_METHOD_OF_DECLARE(socfpga_smp, "altr,socfpga-smp", &socfpga_smp_ops);
+CPU_METHOD_OF_DECLARE(socfpga_a10_smp, "altr,socfpga-a10-smp", &socfpga_a10_smp_ops);
-- 
2.2.1

[PATCH 3/3] ARM: socfpga: dts: add enable-method property for cpu nodes

[dinguyen]

From: Dinh Nguyen <dinguyen@opensource.altera.com>

Add the enable-method property for the cpu node on socfpga.dtsi and
socfpga_arria10.dtsi. This is for CPU_METHOD_OF_DECLARE to use to enable
the secondary core.

Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
---
 arch/arm/boot/dts/socfpga.dtsi         | 1 +
 arch/arm/boot/dts/socfpga_arria10.dtsi | 1 +
 2 files changed, 2 insertions(+)

diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi
index 9b653ed..80f924d 100644
--- a/arch/arm/boot/dts/socfpga.dtsi
+++ b/arch/arm/boot/dts/socfpga.dtsi
@@ -36,6 +36,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "altr,socfpga-smp";
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi
index d025f77..6ceb26e 100644
--- a/arch/arm/boot/dts/socfpga_arria10.dtsi
+++ b/arch/arm/boot/dts/socfpga_arria10.dtsi
@@ -24,6 +24,7 @@
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
+		enable-method = "altr,socfpga-a10-smp";
 
 		cpu@0 {
 			compatible = "arm,cortex-a9";
-- 
2.2.1