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From: Ashok Raj <ashok.raj@intel.com>
To: linux-kernel@vger.kernel.org
Cc: Ashok Raj <ashok.raj@intel.com>,
	linux-edac@vger.kernel.org, Borislav Petkov <bp@suse.de>,
	Tony Luck <tony.luck@intel.com>
Subject: [Patch V1 1/3] x86, mce: Add LMCE definitions.
Date: Fri, 29 May 2015 09:28:00 -0700	[thread overview]
Message-ID: <1432916882-1304-2-git-send-email-ashok.raj@intel.com> (raw)
In-Reply-To: <1432916882-1304-1-git-send-email-ashok.raj@intel.com>

Add required definitions to support Local Machine Check Exceptions.

See http://www.intel.com/sdm Volume 3, System Programming Guide, chapter 15
for more information on MSR's and documentation on Local MCE.

Signed-off-by: Ashok Raj <ashok.raj@intel.com>
---
 arch/x86/include/asm/mce.h            | 5 +++++
 arch/x86/include/uapi/asm/msr-index.h | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/arch/x86/include/asm/mce.h b/arch/x86/include/asm/mce.h
index 1f5a86d..677a408 100644
--- a/arch/x86/include/asm/mce.h
+++ b/arch/x86/include/asm/mce.h
@@ -17,11 +17,16 @@
 #define MCG_EXT_CNT(c)		(((c) & MCG_EXT_CNT_MASK) >> MCG_EXT_CNT_SHIFT)
 #define MCG_SER_P		(1ULL<<24)   /* MCA recovery/new status bits */
 #define MCG_ELOG_P		(1ULL<<26)   /* Extended error log supported */
+#define MCG_LMCE_P		(1ULL<<27)   /* Local machine check supported */
 
 /* MCG_STATUS register defines */
 #define MCG_STATUS_RIPV  (1ULL<<0)   /* restart ip valid */
 #define MCG_STATUS_EIPV  (1ULL<<1)   /* ip points to correct instruction */
 #define MCG_STATUS_MCIP  (1ULL<<2)   /* machine check in progress */
+#define MCG_STATUS_LMCES (1ULL<<3)   /* LMCE signaled */
+
+/* MCG_EXT_CTL register defines */
+#define MCG_EXT_CTL_LMCE_EN (1ULL<<0) /* Enable LMCE */
 
 /* MCi_STATUS register defines */
 #define MCI_STATUS_VAL   (1ULL<<63)  /* valid error */
diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index c469490..e28d5a2 100644
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -56,6 +56,7 @@
 #define MSR_IA32_MCG_CAP		0x00000179
 #define MSR_IA32_MCG_STATUS		0x0000017a
 #define MSR_IA32_MCG_CTL		0x0000017b
+#define MSR_IA32_MCG_EXT_CTL		0x000004d0
 
 #define MSR_OFFCORE_RSP_0		0x000001a6
 #define MSR_OFFCORE_RSP_1		0x000001a7
@@ -379,6 +380,7 @@
 #define FEATURE_CONTROL_LOCKED				(1<<0)
 #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX	(1<<1)
 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX	(1<<2)
+#define FEATURE_CONTROL_LMCE_SUPPORT_ENABLED		(1<<20)
 
 #define MSR_IA32_APICBASE		0x0000001b
 #define MSR_IA32_APICBASE_BSP		(1<<8)
-- 
1.9.1


  reply	other threads:[~2015-05-29 16:47 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2015-05-29 16:27 [Patch V1 0/3] x86 Local Machine Check Exception (LMCE) Ashok Raj
2015-05-29 16:28 ` Ashok Raj [this message]
2015-05-29 16:28 ` [Patch V1 2/3] x86, mce: Add infrastructure required to support LMCE Ashok Raj
2015-05-29 17:35   ` Borislav Petkov
2015-05-29 17:44   ` Borislav Petkov
2015-06-01 17:09     ` Raj, Ashok
2015-06-01 18:48     ` Raj, Ashok
2015-06-01 19:37       ` Borislav Petkov
2015-05-29 16:28 ` [Patch V1 3/3] x86, mce: Handling LMCE events Ashok Raj
2015-05-29 17:36   ` Borislav Petkov

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