From: Barry Song <21cnbao@gmail.com>
To: broonie@kernel.org, gregkh@linuxfoundation.org,
sameo@linux.intel.com, lee.jones@linaro.org
Cc: linux-kernel@vger.kernel.org, workgroup.linux@csr.com,
Guo Zeng <Guo.Zeng@csr.com>, Barry Song <Baohua.Song@csr.com>
Subject: [PATCH 1/3] regmap: irq: add support for chips who have separate unmask registers
Date: Mon, 14 Sep 2015 09:40:08 +0000 [thread overview]
Message-ID: <1442223610-32257-2-git-send-email-21cnbao@gmail.com> (raw)
In-Reply-To: <1442223610-32257-1-git-send-email-21cnbao@gmail.com>
From: Guo Zeng <Guo.Zeng@csr.com>
Some chips have separate unmask registers from mask registers for
some consideration of concurrency SMP write performance. And this
patch adds a flag for it.
An user will be CSR SiRFSoC ARM chips.
Signed-off-by: Guo Zeng <Guo.Zeng@csr.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
---
drivers/base/regmap/regmap-irq.c | 28 ++++++++++++++++++++++++++--
include/linux/regmap.h | 5 +++++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/drivers/base/regmap/regmap-irq.c b/drivers/base/regmap/regmap-irq.c
index 38d1f72..2d21abc 100644
--- a/drivers/base/regmap/regmap-irq.c
+++ b/drivers/base/regmap/regmap-irq.c
@@ -63,6 +63,7 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
struct regmap *map = d->map;
int i, ret;
u32 reg;
+ u32 unmask_offset;
if (d->chip->runtime_pm) {
ret = pm_runtime_get_sync(map->dev);
@@ -82,7 +83,22 @@ static void regmap_irq_sync_unlock(struct irq_data *data)
if (d->chip->mask_invert)
ret = regmap_update_bits(d->map, reg,
d->mask_buf_def[i], ~d->mask_buf[i]);
- else
+ else if (d->chip->unmask_separate) {
+ /* set mask with mask_base register */
+ ret = regmap_update_bits(d->map, reg,
+ d->mask_buf_def[i], ~d->mask_buf[i]);
+ if (ret < 0)
+ dev_err(d->map->dev,
+ "Failed to sync unmasks in %x\n",
+ reg);
+ unmask_offset = d->chip->unmask_base -
+ d->chip->mask_base;
+ /* clear mask with unmask_base register */
+ ret = regmap_update_bits(d->map,
+ reg + unmask_offset,
+ d->mask_buf_def[i],
+ d->mask_buf[i]);
+ } else
ret = regmap_update_bits(d->map, reg,
d->mask_buf_def[i], d->mask_buf[i]);
if (ret != 0)
@@ -339,6 +355,7 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
int i;
int ret = -ENOMEM;
u32 reg;
+ u32 unmask_offset;
if (chip->num_regs <= 0)
return -EINVAL;
@@ -420,7 +437,14 @@ int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags,
if (chip->mask_invert)
ret = regmap_update_bits(map, reg,
d->mask_buf[i], ~d->mask_buf[i]);
- else
+ else if (d->chip->unmask_separate) {
+ unmask_offset = d->chip->unmask_base -
+ d->chip->mask_base;
+ ret = regmap_update_bits(d->map,
+ reg + unmask_offset,
+ d->mask_buf[i],
+ d->mask_buf[i]);
+ } else
ret = regmap_update_bits(map, reg,
d->mask_buf[i], d->mask_buf[i]);
if (ret != 0) {
diff --git a/include/linux/regmap.h b/include/linux/regmap.h
index 8fc0bfd..bb5ba97 100644
--- a/include/linux/regmap.h
+++ b/include/linux/regmap.h
@@ -800,12 +800,15 @@ struct regmap_irq {
*
* @status_base: Base status register address.
* @mask_base: Base mask register address.
+ * @unmask_base: Base unmask register address. for chips who have
+ * separate mask and unmask registers
* @ack_base: Base ack address. If zero then the chip is clear on read.
* Using zero value is possible with @use_ack bit.
* @wake_base: Base address for wake enables. If zero unsupported.
* @irq_reg_stride: Stride to use for chips where registers are not contiguous.
* @init_ack_masked: Ack all masked interrupts once during initalization.
* @mask_invert: Inverted mask register: cleared bits are masked out.
+ * @unmask_separate: unmask is separate register from mask.
* @use_ack: Use @ack register even if it is zero.
* @wake_invert: Inverted wake register: cleared bits are wake enabled.
* @runtime_pm: Hold a runtime PM lock on the device when accessing it.
@@ -820,11 +823,13 @@ struct regmap_irq_chip {
unsigned int status_base;
unsigned int mask_base;
+ unsigned int unmask_base;
unsigned int ack_base;
unsigned int wake_base;
unsigned int irq_reg_stride;
bool init_ack_masked:1;
bool mask_invert:1;
+ bool unmask_separate:1;
bool use_ack:1;
bool wake_invert:1;
bool runtime_pm:1;
--
1.9.1
next prev parent reply other threads:[~2015-09-14 9:32 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-09-14 9:40 [PATCH 0/3] add CSR SiRFSoC power control module MFD driver Barry Song
2015-09-14 9:40 ` Barry Song [this message]
2015-09-16 19:37 ` [PATCH 1/3] regmap: irq: add support for chips who have separate unmask registers Mark Brown
2015-09-14 9:40 ` [PATCH 2/3] regmap: irq: add ack_invert flag for chips using cleared bits as ack Barry Song
2015-09-16 19:39 ` Mark Brown
2015-09-14 9:40 ` [PATCH 3/3] mfd: add CSR SiRFSoC on-chip power management module driver Barry Song
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1442223610-32257-2-git-send-email-21cnbao@gmail.com \
--to=21cnbao@gmail.com \
--cc=Baohua.Song@csr.com \
--cc=Guo.Zeng@csr.com \
--cc=broonie@kernel.org \
--cc=gregkh@linuxfoundation.org \
--cc=lee.jones@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=sameo@linux.intel.com \
--cc=workgroup.linux@csr.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®