* [PATCH v3] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC
@ 2015-10-30 17:08 J. German Rivera
2015-10-30 18:22 ` Stuart Yoder
0 siblings, 1 reply; 2+ messages in thread
From: J. German Rivera @ 2015-10-30 17:08 UTC (permalink / raw)
To: robh+dt, mark.rutland, devicetree, linux-arm-kernel, linux-kernel
Cc: bhupesh.sharma, stuart.yoder, leoli, J. German Rivera
Added sys-reboot node to the FSL's LS2085A SoC DT to leverage
the ARM-generic reboot mechanism for this SoC. This mechanism
is enabled through CONFIG_POWER_RESET_SYSCON.
Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
---
CHANGE HISTORY:
Changes in v2:
- Addressed comment form Stuart Yoder:
* Removed "@<address>" from reboot node
Changes in v3:
- Addressed comment form Stuart Yoder:
* Expose only the reset register
arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
index e281ceb..5e3d894 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
@@ -131,6 +131,18 @@
interrupts = <1 9 0x4>;
};
+ rstcr: rstcr@1E60000 {
+ compatible = "syscon";
+ reg = <0x0 0x1E60000 0x0 0x4>;
+ };
+
+ reboot {
+ compatible ="syscon-reboot";
+ regmap = <&rstcr>;
+ offset = <0x0>;
+ mask = <0x2>;
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
--
2.3.3
^ permalink raw reply [flat|nested] 2+ messages in thread
* RE: [PATCH v3] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC
2015-10-30 17:08 [PATCH v3] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC J. German Rivera
@ 2015-10-30 18:22 ` Stuart Yoder
0 siblings, 0 replies; 2+ messages in thread
From: Stuart Yoder @ 2015-10-30 18:22 UTC (permalink / raw)
To: Jose Rivera, robh+dt, mark.rutland, devicetree, linux-arm-kernel,
linux-kernel
Cc: Sharma Bhupesh, Li Leo, Jose Rivera
> -----Original Message-----
> From: J. German Rivera [mailto:German.Rivera@freescale.com]
> Sent: Friday, October 30, 2015 12:08 PM
> To: robh+dt@kernel.org; mark.rutland@arm.com; devicetree@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org
> Cc: Sharma Bhupesh-B45370; Yoder Stuart-B08248; Li Yang-Leo-R58472; Rivera Jose-B46482
> Subject: [PATCH v3] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC
>
> Added sys-reboot node to the FSL's LS2085A SoC DT to leverage
> the ARM-generic reboot mechanism for this SoC. This mechanism
> is enabled through CONFIG_POWER_RESET_SYSCON.
>
> Signed-off-by: J. German Rivera <German.Rivera@freescale.com>
> ---
> CHANGE HISTORY:
>
> Changes in v2:
> - Addressed comment form Stuart Yoder:
> * Removed "@<address>" from reboot node
>
> Changes in v3:
> - Addressed comment form Stuart Yoder:
> * Expose only the reset register
>
> arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
> index e281ceb..5e3d894 100644
> --- a/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
> +++ b/arch/arm64/boot/dts/freescale/fsl-ls2085a.dtsi
> @@ -131,6 +131,18 @@
> interrupts = <1 9 0x4>;
> };
>
> + rstcr: rstcr@1E60000 {
> + compatible = "syscon";
> + reg = <0x0 0x1E60000 0x0 0x4>;
> + };
> +
> + reboot {
> + compatible ="syscon-reboot";
> + regmap = <&rstcr>;
> + offset = <0x0>;
> + mask = <0x2>;
> + };
> +
> timer {
> compatible = "arm,armv8-timer";
> interrupts = <1 13 0x8>, /* Physical Secure PPI, active-low */
German, the other thing I just noticed that I had mentioned on
v1 of the patch was that the device tree has been renamed, so
fsl-ls2085a.dtsi no longer exists.
You need to rebase this on top of:
git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc.git
branch: for-next
Thanks,
Stuart
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2015-10-30 17:08 [PATCH v3] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC J. German Rivera
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