Re: Unreliable register being read in max310x UART driver

Re: Unreliable register being read in max310x UART driver

[Alexander Shiyan]

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Hello.

> Понедельник,  2 ноября 2015, 10:24 -05:00 от Alexander Shi <alexandershi@nanometrics.ca>:
> 
> Hello all,
>  
> The datasheet for MAX3107 UART ( http://datasheets.maximintegrated.com/en/ds/MAX3107.pdf ) was updated in February 2015 with a notice that the RxFIFOLvl register may be inaccurate if read while being updated. The respective max310x.c driver in the kernel actively makes use of the RxFIFOLvl register, but has not been updated since the notice was posted. Does anyone have a workaround to this bug?
>  
> The notice was phrased as follows:
> “The RxFIFOLvl register represents the current number of words in the receive FIFO whenever the receive UART is idle. When the receive UART actively receives characters, the value in this register can sometimes be inaccurate if this register is read at the same time that the receive UART updates the receive FIFO. To manage the receive FIFO even when the receive UART is active, do not use this register to determine receive FIFO state. Use the RFIFOEmptyInt bit, the RxTrgInt bit, and the RTimeOut bit instead.”
>  
> Thanks,
> Alex

On my opinion this should not be a problem.
The RX interrupt will be triggered once again if we lost RX level value.
Anyway, you can add one check after reading rxfifolvl register:
  if (!(ists & MAX310X_IRQ_RXEMPTY_BIT))
    rxlen = 1;

Thanks.
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Unreliable register being read in max310x UART driver

[Alexander Shi]

Hello all,



The datasheet for MAX3107 UART
(http://datasheets.maximintegrated.com/en/ds/MAX3107.pdf) was updated
in February 2015 with a notice that the RxFIFOLvl register may be
inaccurate if read while being updated. The respective max310x.c
driver actively makes use of the RxFIFOLvl register, but has not been
updated since the notice was posted. Does anyone have a workaround to
this bug?



The notice was phrased as follows:

“The RxFIFOLvl register represents the current number of words in the
receive FIFO whenever the receive UART is idle. When the receive UART
actively receives characters, the value in this register can sometimes
be inaccurate if this register is read at the same time that the
receive UART updates the receive FIFO. To manage the receive FIFO even
when the receive UART is active, do not use this register to determine
receive FIFO state. Use the RFIFOEmptyInt bit, the RxTrgInt bit, and
the RTimeOut bit instead.”



Thanks,

Alex