[PATCH net-next 0/2] r8169:Update RTL8168H PHY parameters

[PATCH net-next 0/2] r8169:Update RTL8168H PHY parameters

[Chunhao Lin]

Fix typo in setting PHY parameter and update the way of reading PHY register
"rg_saw_cnt".

Chunhao Lin (2):
  r8169:Fix typo in setting RTL8168H PHY parameter
  r8169:Update the way of reading RTL8168H PHY register "rg_saw_cnt"

 drivers/net/ethernet/realtek/r8169.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

-- 
1.9.1

[PATCH net-next 1/2] r8169:Fix typo in setting RTL8168H PHY parameter

[Chunhao Lin]

In function "rtl8168h_2_hw_phy_config", there is a typo in setting
RTL8168H PHY parameter.

Signed-off-by: Chunhao Lin <hau@realtek.com>
---
 drivers/net/ethernet/realtek/r8169.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 79ef799..11cc32b 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -3947,7 +3947,7 @@ static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
 	data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
 
 	if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
-	    (ioffset_p1 != 0x0f) || (ioffset_p0 == 0x0f)) {
+	    (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
 		rtl_writephy(tp, 0x1f, 0x0bcf);
 		rtl_writephy(tp, 0x16, data);
 		rtl_writephy(tp, 0x1f, 0x0000);
-- 
1.9.1

[PATCH net-next 2/2] r8169:Update the way of reading RTL8168H PHY register "rg_saw_cnt"

[Chunhao Lin]

The vlaue of RTL8168H PHY register "rg_saw_cnt" only valid from bit0 to bit13.
When read this register, add bitwise-anding its value with 0x3fff.

Signed-off-by: Chunhao Lin <hau@realtek.com>
---
 drivers/net/ethernet/realtek/r8169.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 11cc32b..58365bc 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -6136,7 +6136,7 @@ static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
 	rtl_pcie_state_l2l3_enable(tp, false);
 
 	rtl_writephy(tp, 0x1f, 0x0c42);
-	rg_saw_cnt = rtl_readphy(tp, 0x13);
+	rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
 	rtl_writephy(tp, 0x1f, 0x0000);
 	if (rg_saw_cnt > 0) {
 		u16 sw_cnt_1ms_ini;
-- 
1.9.1

Re: [PATCH net-next 0/2] r8169:Update RTL8168H PHY parameters

[David Miller]

From: Chunhao Lin <hau@realtek.com>
Date: Thu, 24 Dec 2015 21:15:25 +0800

> Fix typo in setting PHY parameter and update the way of reading PHY register
> "rg_saw_cnt".

Series applied, thanks.