From: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com>
To: <bhelgaas@google.com>, <soren.brinkmann@xilinx.com>,
<christophe.jaillet@wanadoo.fr>, <grygorii.strashko@ti.com>,
<yinghai@kernel.org>, <lorenzo.pieralisi@arm.com>,
<fengguang.wu@intel.com>, <michal.simek@xilinx.com>,
<arnd@arndb.de>
Cc: <linux-arm-kernel@lists.infradead.org>,
<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<rgummal@xilinx.com>, Bharat Kumar Gogada <bharatku@xilinx.com>
Subject: [PATCH 2/6] PCI: Xilinx : Clear interrupt register for invalid interrupt.
Date: Thu, 1 Sep 2016 15:44:42 +0530 [thread overview]
Message-ID: <1472724886-28301-2-git-send-email-bharatku@xilinx.com> (raw)
In-Reply-To: <1472724886-28301-1-git-send-email-bharatku@xilinx.com>
The interrupt decode register is not being cleared if
an invalid interrupt arises. This patch adds checks
and clears decode register in this case.
Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
---
drivers/pci/host/pcie-xilinx.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-xilinx.c b/drivers/pci/host/pcie-xilinx.c
index bd64677..de1c758 100644
--- a/drivers/pci/host/pcie-xilinx.c
+++ b/drivers/pci/host/pcie-xilinx.c
@@ -434,7 +434,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
/* Check whether interrupt valid */
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
- return IRQ_HANDLED;
+ goto error;
}
if (!(val & XILINX_PCIE_RPIFR1_MSI_INTR)) {
@@ -456,7 +456,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
dev_warn(port->dev, "RP Intr FIFO1 read error\n");
- return IRQ_HANDLED;
+ goto error;
}
if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
@@ -501,6 +501,7 @@ static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
if (status & XILINX_PCIE_INTR_MST_ERRP)
dev_warn(port->dev, "Master error poison\n");
+error:
/* Clear the Interrupt Decode register */
pcie_write(port, status, XILINX_PCIE_REG_IDR);
--
2.1.1
next prev parent reply other threads:[~2016-09-01 10:15 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-01 10:14 [PATCH 1/6] PCI: xilinx: Keep both legacy and MSI interrupt references Bharat Kumar Gogada
2016-09-01 10:14 ` Bharat Kumar Gogada [this message]
2016-09-01 10:14 ` [PATCH 3/6] PCI: Xilinx: Clear correct msi set bit Bharat Kumar Gogada
2016-09-01 10:14 ` [PATCH 4/6] PCI: Xilinx: Dispose MSI virtual irq Bharat Kumar Gogada
2016-09-01 10:14 ` [PATCH 5/6] PCI: Xilinx: Read more than one function per device Bharat Kumar Gogada
2016-09-01 10:14 ` [PATCH 6/6] Microblaze: Modify microblaze pci specific code to support multidomain Bharat Kumar Gogada
2016-09-12 22:21 ` [PATCH 1/6] PCI: xilinx: Keep both legacy and MSI interrupt references Bjorn Helgaas
2016-09-13 15:56 ` Bjorn Helgaas
2016-09-14 15:32 ` Bharat Kumar Gogada
2016-09-14 19:17 ` Bjorn Helgaas
2016-09-15 5:09 ` Bharat Kumar Gogada
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