From: Matt Redfearn <matt.redfearn@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>,
Matt Redfearn <matt.redfearn@imgtec.com>,
Adam Buchbinder <adam.buchbinder@gmail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
<linux-kernel@vger.kernel.org>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH v2 06/12] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier
Date: Wed, 7 Sep 2016 10:45:14 +0100 [thread overview]
Message-ID: <1473241520-14917-7-git-send-email-matt.redfearn@imgtec.com> (raw)
In-Reply-To: <1473241520-14917-1-git-send-email-matt.redfearn@imgtec.com>
Since R2 of the MIPS architecture, SYNC(0x10) has been an optional but
architecturally defined ordering barrier. If a CPU does not implement it,
the arch specifies that it must fall back to SYNC(0).
In places where we require that the instruction stream not be reordered,
but do not require that loads / stores are gloablly completed, use the
defined standard sync stype.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2: None
arch/mips/kernel/pm-cps.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 7e8d4aa22233..d7037fe00d1c 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -76,7 +76,6 @@ static struct uasm_reloc relocs[32] __initdata;
/* CPU dependant sync types */
static unsigned stype_intervention;
static unsigned stype_memory;
-static unsigned stype_ordering;
enum mips_reg {
zero, at, v0, v1, a0, a1, a2, a3,
@@ -406,7 +405,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
if (coupled_coherence) {
/* Increment ready_count */
- uasm_i_sync(&p, stype_ordering);
+ uasm_i_sync(&p, STYPE_SYNC_MB);
uasm_build_label(&l, p, lbl_incready);
uasm_i_ll(&p, t1, 0, r_nc_count);
uasm_i_addiu(&p, t2, t1, 1);
@@ -415,7 +414,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_addiu(&p, t1, t1, 1);
/* Barrier ensuring all CPUs see the updated r_nc_count value */
- uasm_i_sync(&p, stype_ordering);
+ uasm_i_sync(&p, STYPE_SYNC_MB);
/*
* If this is the last VPE to become ready for non-coherence
@@ -568,7 +567,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
if (coupled_coherence && (state == CPS_PM_NC_WAIT)) {
/* Decrement ready_count */
uasm_build_label(&l, p, lbl_decready);
- uasm_i_sync(&p, stype_ordering);
+ uasm_i_sync(&p, STYPE_SYNC_MB);
uasm_i_ll(&p, t1, 0, r_nc_count);
uasm_i_addiu(&p, t2, t1, -1);
uasm_i_sc(&p, t2, 0, r_nc_count);
@@ -576,7 +575,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_i_andi(&p, v0, t1, (1 << fls(smp_num_siblings)) - 1);
/* Barrier ensuring all CPUs see the updated r_nc_count value */
- uasm_i_sync(&p, stype_ordering);
+ uasm_i_sync(&p, STYPE_SYNC_MB);
}
if (coupled_coherence && (state == CPS_PM_CLOCK_GATED)) {
@@ -598,7 +597,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
uasm_build_label(&l, p, lbl_secondary_cont);
/* Barrier ensuring all CPUs see the updated r_nc_count value */
- uasm_i_sync(&p, stype_ordering);
+ uasm_i_sync(&p, STYPE_SYNC_MB);
}
/* The core is coherent, time to return to C code */
@@ -677,7 +676,6 @@ static int __init cps_pm_init(void)
case CPU_I6400:
stype_intervention = 0x2;
stype_memory = 0x3;
- stype_ordering = 0x10;
break;
default:
--
2.7.4
next prev parent reply other threads:[~2016-09-07 9:47 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-07 9:45 [PATCH v2 00/12] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 01/12] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 02/12] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 03/12] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 04/12] MIPS: pm-cps: Update comments on barrier instructions Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 05/12] MIPS: Barrier: Add definitions of SYNC stype values Matt Redfearn
2016-09-07 11:24 ` Peter Zijlstra
2016-09-07 11:31 ` Peter Zijlstra
2016-09-07 9:45 ` Matt Redfearn [this message]
2016-09-07 9:45 ` [PATCH v2 07/12] MIPS: pm-cps: Use MIPS standard completion barrier Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 08/12] MIPS: pm-cps: Remove selection of sync types Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 09/12] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 10/12] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 11/12] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 12/12] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs Matt Redfearn
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