From: Matt Redfearn <matt.redfearn@imgtec.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: <linux-mips@linux-mips.org>,
Matt Redfearn <matt.redfearn@imgtec.com>,
Adam Buchbinder <adam.buchbinder@gmail.com>,
Masahiro Yamada <yamada.masahiro@socionext.com>,
Kees Cook <keescook@chromium.org>, <linux-kernel@vger.kernel.org>,
Markos Chandras <markos.chandras@imgtec.com>,
Paul Burton <paul.burton@imgtec.com>
Subject: [PATCH v2 08/12] MIPS: pm-cps: Remove selection of sync types
Date: Wed, 7 Sep 2016 10:45:16 +0100 [thread overview]
Message-ID: <1473241520-14917-9-git-send-email-matt.redfearn@imgtec.com> (raw)
In-Reply-To: <1473241520-14917-1-git-send-email-matt.redfearn@imgtec.com>
Instead of selecting an implementation or vendor specific sync type for
the required sync operations, always use the architecturally mandated
sync types which previous patches have put in place. The selection of
special sync types is now redundant an can be removed.
Signed-off-by: Matt Redfearn <matt.redfearn@imgtec.com>
Reviewed-by: Paul Burton <paul.burton@imgtec.com>
---
Changes in v2:
Use architecturally standard lightweight sync types rather than
selecting CPU specific ones.
arch/mips/kernel/pm-cps.c | 19 -------------------
1 file changed, 19 deletions(-)
diff --git a/arch/mips/kernel/pm-cps.c b/arch/mips/kernel/pm-cps.c
index 953ff0db9061..b3a7d36ada5a 100644
--- a/arch/mips/kernel/pm-cps.c
+++ b/arch/mips/kernel/pm-cps.c
@@ -73,10 +73,6 @@ DEFINE_PER_CPU_ALIGNED(struct mips_static_suspend_state, cps_cpu_state);
static struct uasm_label labels[32] __initdata;
static struct uasm_reloc relocs[32] __initdata;
-/* CPU dependant sync types */
-static unsigned stype_intervention;
-static unsigned stype_memory;
-
enum mips_reg {
zero, at, v0, v1, a0, a1, a2, a3,
t0, t1, t2, t3, t4, t5, t6, t7,
@@ -667,21 +663,6 @@ static int __init cps_pm_init(void)
unsigned cpu;
int err;
- /* Detect appropriate sync types for the system */
- switch (current_cpu_data.cputype) {
- case CPU_INTERAPTIV:
- case CPU_PROAPTIV:
- case CPU_M5150:
- case CPU_P5600:
- case CPU_I6400:
- stype_intervention = 0x2;
- stype_memory = 0x3;
- break;
-
- default:
- pr_warn("Power management is using heavyweight sync 0\n");
- }
-
/* A CM is required for all non-coherent states */
if (!mips_cm_present()) {
pr_warn("pm-cps: no CM, non-coherent states unavailable\n");
--
2.7.4
next prev parent reply other threads:[~2016-09-07 9:46 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-09-07 9:45 [PATCH v2 00/12] MIPS CPC fixup and CPU Idle for MIPSr6 CPUs Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 01/12] MIPS: CPC: Convert bare 'unsigned' to 'unsigned int' Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 02/12] MIPS: CPC: Avoid lock when MIPS CM >= 3 is present Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 03/12] MIPS: pm-cps: Change FSB workaround to CPU blacklist Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 04/12] MIPS: pm-cps: Update comments on barrier instructions Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 05/12] MIPS: Barrier: Add definitions of SYNC stype values Matt Redfearn
2016-09-07 11:24 ` Peter Zijlstra
2016-09-07 11:31 ` Peter Zijlstra
2016-09-07 9:45 ` [PATCH v2 06/12] MIPS: pm-cps: Use MIPS standard lightweight ordering barrier Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 07/12] MIPS: pm-cps: Use MIPS standard completion barrier Matt Redfearn
2016-09-07 9:45 ` Matt Redfearn [this message]
2016-09-07 9:45 ` [PATCH v2 09/12] MIPS: pm-cps: Add MIPSr6 CPU support Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 10/12] MIPS: pm-cps: Support CM3 changes to Coherence Enable Register Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 11/12] MIPS: SMP: Wrap call to mips_cpc_lock_other in mips_cm_lock_other Matt Redfearn
2016-09-07 9:45 ` [PATCH v2 12/12] cpuidle: cpuidle-cps: Enable use with MIPSr6 CPUs Matt Redfearn
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