* [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake RAPL support @ 2016-09-09 17:53 Harry Pan 2016-09-09 17:53 ` [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell " Harry Pan 0 siblings, 1 reply; 5+ messages in thread From: Harry Pan @ 2016-09-09 17:53 UTC (permalink / raw) To: LKML Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, peterz, bp, dave.hansen, srinivas.pandruvada This patch enables RAPL counters (energy consumption counters) support for Intel Apollo Lake (Goldmont) processors (Model 92): RAPL of Goldmont, unlikes ESU increment of Silvermont/Airmont, it likes the Haswell microarchitecture in 1/2^ESU joules and supports power domains in PP0/PP1/PKG/RAM. ESU and power domains refer to Intel Software Developers' Manual, Vol. 3C, Order No. 325384, Table 35-12. Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index 2886593..f7924640 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -765,6 +765,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), + + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), {}, }; -- 2.6.6 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell RAPL support 2016-09-09 17:53 [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake RAPL support Harry Pan @ 2016-09-09 17:53 ` Harry Pan 2016-09-09 21:02 ` kbuild test robot 0 siblings, 1 reply; 5+ messages in thread From: Harry Pan @ 2016-09-09 17:53 UTC (permalink / raw) To: LKML Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, peterz, bp, ray.huang, srinivas.pandruvada This patch enables RAPL counters (energy consumption counters) support for Intel Baytrail and Braswell processors (Model 55 and 76): The Silvermont/Airmont microarchitecture actually uses fixed energy status unit (ESU) in smallest unit of microjoule, this patch adds quirk for these Atom processors (BYT/BSW) to calculate energy increment in 2^ESU microjoules. ESU and power domains refer to Intel Software Developers' Manual, Vol. 3C, Order No. 325384, Table 35-8. v2: simplify setting rapl_hw_unit[] to reduce runtime overhead. v3: refine multiple quirks in rapl_check_hw_unit(). Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 This patch also enables multiple quirks. Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 83 +++++++++++++++++++++++++++++++++++--------- 1 file changed, 67 insertions(+), 16 deletions(-) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index f7924640..3786574 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -110,6 +110,10 @@ static const char *const rapl_domain_names[NR_RAPL_DOMAINS] __initconst = { #define RAPL_IDX_KNL (1<<RAPL_IDX_PKG_NRG_STAT|\ 1<<RAPL_IDX_RAM_NRG_STAT) +/* Baytrail/Braswell clients have PP0, PKG */ +#define RAPL_IDX_BYT (1<<RAPL_IDX_PP0_NRG_STAT|\ + 1<<RAPL_IDX_PKG_NRG_STAT) + /* * event code: LSB 8 bits, passed in attr->config * any other bit is reserved @@ -136,6 +140,12 @@ static struct perf_pmu_events_attr event_attr_##v = { \ .event_str = str, \ }; +enum rapl_quirk { + RAPL_NO_QUIRK = 0, + RAPL_HSX_QUIRK, + RAPL_BYT_QUIRK, +}; + struct rapl_pmu { raw_spinlock_t lock; int n_active; @@ -452,6 +462,14 @@ RAPL_EVENT_ATTR_STR(energy-ram.scale, rapl_ram_scale, "2.3283064365386962890 RAPL_EVENT_ATTR_STR(energy-gpu.scale, rapl_gpu_scale, "2.3283064365386962890625e-10"); RAPL_EVENT_ATTR_STR(energy-psys.scale, rapl_psys_scale, "2.3283064365386962890625e-10"); +/* + * Some Atom series processors (BYT/BSW) have fixed + * energy status unit (ESU) in smallest unit of microjoule, + * and its increment is in 2^ESU microjoules. + */ +RAPL_EVENT_ATTR_STR(energy-cores.scale, rapl_byt_cores_scale, "1.0e-6"); +RAPL_EVENT_ATTR_STR(energy-pkg.scale, rapl_byt_pkg_scale, "1.0e-6"); + static struct attribute *rapl_events_srv_attr[] = { EVENT_PTR(rapl_cores), EVENT_PTR(rapl_pkg), @@ -533,6 +551,18 @@ static struct attribute *rapl_events_knl_attr[] = { NULL, }; +static struct attribute *rapl_events_byt_attr[] = { + EVENT_PTR(rapl_cores), + EVENT_PTR(rapl_pkg), + + EVENT_PTR(rapl_cores_unit), + EVENT_PTR(rapl_pkg_unit), + + EVENT_PTR(rapl_byt_cores_scale), + EVENT_PTR(rapl_byt_pkg_scale), + NULL, +}; + static struct attribute_group rapl_pmu_events_group = { .name = "events", .attrs = NULL, /* patched at runtime */ @@ -617,7 +647,7 @@ static int rapl_cpu_prepare(unsigned int cpu) return 0; } -static int rapl_check_hw_unit(bool apply_quirk) +static int rapl_check_hw_unit(enum rapl_quirk apply_quirk) { u64 msr_rapl_power_unit_bits; int i; @@ -628,14 +658,27 @@ static int rapl_check_hw_unit(bool apply_quirk) for (i = 0; i < NR_RAPL_DOMAINS; i++) rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; - /* - * DRAM domain on HSW server and KNL has fixed energy unit which can be - * different than the unit from power unit MSR. See - * "Intel Xeon Processor E5-1600 and E5-2600 v3 Product Families, V2 - * of 2. Datasheet, September 2014, Reference Number: 330784-001 " - */ - if (apply_quirk) + switch (apply_quirk) { + case RAPL_HSX_QUIRK: + /* + * DRAM domain on HSW server and KNL has fixed energy unit + * which can be different than the unit from power unit MSR. + * See "Intel Xeon Processor E5-1600 and E5-2600 v3 Product + * Families, V2 of 2. Datasheet, September 2014, + * Reference Number: 330784-001" + */ rapl_hw_unit[RAPL_IDX_RAM_NRG_STAT] = 16; + break; + case RAPL_BYT_QUIRK: + /* + * Some Atom processors (BYT/BSW) have 2^ESU microjoules + * increment, refer to Software Developers' Manual, Vol. 3C, + * Order No. 325384, Table 35-8 of MSR_RAPL_POWER_UNIT. + */ + for (i = 0; i < NR_RAPL_DOMAINS; i++) + rapl_hw_unit[i] = 32 - rapl_hw_unit[i]; + break; + } /* * Calculate the timer rate: @@ -702,47 +745,53 @@ static int __init init_rapl_pmus(void) { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, (unsigned long)&init } struct intel_rapl_init_fun { - bool apply_quirk; + enum rapl_quirk apply_quirk; int cntr_mask; struct attribute **attrs; }; static const struct intel_rapl_init_fun snb_rapl_init __initconst = { - .apply_quirk = false, + .apply_quirk = RAPL_NO_QUIRK, .cntr_mask = RAPL_IDX_CLN, .attrs = rapl_events_cln_attr, }; static const struct intel_rapl_init_fun hsx_rapl_init __initconst = { - .apply_quirk = true, + .apply_quirk = RAPL_HSX_QUIRK, .cntr_mask = RAPL_IDX_SRV, .attrs = rapl_events_srv_attr, }; static const struct intel_rapl_init_fun hsw_rapl_init __initconst = { - .apply_quirk = false, + .apply_quirk = RAPL_NO_QUIRK, .cntr_mask = RAPL_IDX_HSW, .attrs = rapl_events_hsw_attr, }; static const struct intel_rapl_init_fun snbep_rapl_init __initconst = { - .apply_quirk = false, + .apply_quirk = RAPL_NO_QUIRK, .cntr_mask = RAPL_IDX_SRV, .attrs = rapl_events_srv_attr, }; static const struct intel_rapl_init_fun knl_rapl_init __initconst = { - .apply_quirk = true, + .apply_quirk = RAPL_HSX_QUIRK, .cntr_mask = RAPL_IDX_KNL, .attrs = rapl_events_knl_attr, }; static const struct intel_rapl_init_fun skl_rapl_init __initconst = { - .apply_quirk = false, + .apply_quirk = RAPL_NO_QUIRK, .cntr_mask = RAPL_IDX_SKL_CLN, .attrs = rapl_events_skl_attr, }; +static const struct intel_rapl_init_fun byt_rapl_init __initconst = { + .apply_quirk = RAPL_BYT_QUIRK, + .cntr_mask = RAPL_IDX_BYT, + .attrs = rapl_events_byt_attr, +}; + static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE, snb_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SANDYBRIDGE_X, snbep_rapl_init), @@ -766,6 +815,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_SILVERMONT1, byt_rapl_init), + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_AIRMONT, byt_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), {}, }; @@ -776,7 +827,7 @@ static int __init rapl_pmu_init(void) { const struct x86_cpu_id *id; struct intel_rapl_init_fun *rapl_init; - bool apply_quirk; + enum rapl_quirk apply_quirk; int ret; id = x86_match_cpu(rapl_cpu_match); -- 2.6.6 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell RAPL support 2016-09-09 17:53 ` [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell " Harry Pan @ 2016-09-09 21:02 ` kbuild test robot 0 siblings, 0 replies; 5+ messages in thread From: kbuild test robot @ 2016-09-09 21:02 UTC (permalink / raw) To: Harry Pan Cc: kbuild-all, LKML, gs0622, Harry Pan, tglx, mingo, hpa, x86, peterz, bp, ray.huang, srinivas.pandruvada [-- Attachment #1: Type: text/plain, Size: 2196 bytes --] Hi Harry, [auto build test WARNING on v4.8-rc5] [also build test WARNING on next-20160909] [cannot apply to tip/x86/core] [if your patch is applied to the wrong git tree, please drop us a note to help improve the system] [Suggest to use git(>=2.9.0) format-patch --base=<commit> (or --base=auto for convenience) to record what (public, well-known) commit your patch series was built on] [Check https://git-scm.com/docs/git-format-patch for more information] url: https://github.com/0day-ci/linux/commits/Harry-Pan/perf-x86-rapl-Enable-Apollo-Lake-RAPL-support/20160910-015650 config: x86_64-randconfig-x008-201636 (attached as .config) compiler: gcc-6 (Debian 6.1.1-9) 6.1.1 20160705 reproduce: # save the attached .config to linux build tree make ARCH=x86_64 All warnings (new ones prefixed by >>): arch/x86/events/intel/rapl.c: In function 'rapl_check_hw_unit': >> arch/x86/events/intel/rapl.c:661:2: warning: enumeration value 'RAPL_NO_QUIRK' not handled in switch [-Wswitch] switch (apply_quirk) { ^~~~~~ vim +/RAPL_NO_QUIRK +661 arch/x86/events/intel/rapl.c 645 rapl_hrtimer_init(pmu); 646 rapl_pmus->pmus[topology_logical_package_id(cpu)] = pmu; 647 return 0; 648 } 649 650 static int rapl_check_hw_unit(enum rapl_quirk apply_quirk) 651 { 652 u64 msr_rapl_power_unit_bits; 653 int i; 654 655 /* protect rdmsrl() to handle virtualization */ 656 if (rdmsrl_safe(MSR_RAPL_POWER_UNIT, &msr_rapl_power_unit_bits)) 657 return -1; 658 for (i = 0; i < NR_RAPL_DOMAINS; i++) 659 rapl_hw_unit[i] = (msr_rapl_power_unit_bits >> 8) & 0x1FULL; 660 > 661 switch (apply_quirk) { 662 case RAPL_HSX_QUIRK: 663 /* 664 * DRAM domain on HSW server and KNL has fixed energy unit 665 * which can be different than the unit from power unit MSR. 666 * See "Intel Xeon Processor E5-1600 and E5-2600 v3 Product 667 * Families, V2 of 2. Datasheet, September 2014, 668 * Reference Number: 330784-001" 669 */ --- 0-DAY kernel test infrastructure Open Source Technology Center https://lists.01.org/pipermail/kbuild-all Intel Corporation [-- Attachment #2: .config.gz --] [-- Type: application/octet-stream, Size: 21126 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake RAPL support @ 2016-09-09 15:01 Harry Pan 0 siblings, 0 replies; 5+ messages in thread From: Harry Pan @ 2016-09-09 15:01 UTC (permalink / raw) To: LKML Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, peterz, bp, srinivas.pandruvada, ray.huang This patch enables RAPL counters (energy consumption counters) support for Intel Apollo Lake (Goldmont) processors (Model 92): RAPL of Goldmont, unlikes ESU increment of Silvermont/Airmont, it likes the Haswell microarchitecture in 1/2^ESU joules and supports power domains in PP0/PP1/PKG/RAM. ESU and power domains refer to Intel Software Developers' Manual, Vol. 3C, Order No. 325384, Table 35-12. Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index 2886593..f7924640 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -765,6 +765,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), + + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), {}, }; -- 2.6.6 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake RAPL support @ 2016-09-08 9:08 Harry Pan 0 siblings, 0 replies; 5+ messages in thread From: Harry Pan @ 2016-09-08 9:08 UTC (permalink / raw) To: LKML Cc: gs0622, Harry Pan, tglx, mingo, hpa, x86, peterz, bp, srinivas.pandruvada This patch enables RAPL counters (energy consumption counters) support for Intel Apollo Lake (Goldmont) processors (Model 92): RAPL of Goldmont, unlikes ESU increment of Silvermont/Airmont, it likes the Haswell microarchitecture in 1/2^ESU joules and supports power domains in PP0/PP1/PKG/RAM. ESU and power domains refer to Intel Software Developers' Manual, Vol. 3C, Order No. 325384, Table 35-12. Usage example: $ perf list $ perf stat -a -e power/energy-cores/,power/energy-pkg/ sleep 10 Signed-off-by: Harry Pan <harry.pan@intel.com> --- arch/x86/events/intel/rapl.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/x86/events/intel/rapl.c b/arch/x86/events/intel/rapl.c index 2886593..f7924640 100644 --- a/arch/x86/events/intel/rapl.c +++ b/arch/x86/events/intel/rapl.c @@ -765,6 +765,8 @@ static const struct x86_cpu_id rapl_cpu_match[] __initconst = { X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_MOBILE, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_DESKTOP, skl_rapl_init), X86_RAPL_MODEL_MATCH(INTEL_FAM6_SKYLAKE_X, hsx_rapl_init), + + X86_RAPL_MODEL_MATCH(INTEL_FAM6_ATOM_GOLDMONT, hsw_rapl_init), {}, }; -- 2.6.6 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2016-09-09 21:03 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2016-09-09 17:53 [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake RAPL support Harry Pan 2016-09-09 17:53 ` [PATCH 2/2] perf/x86/rapl: Enable Baytrail/Braswell " Harry Pan 2016-09-09 21:02 ` kbuild test robot -- strict thread matches above, loose matches on Subject: below -- 2016-09-09 15:01 [PATCH 1/2] perf/x86/rapl: Enable Apollo Lake " Harry Pan 2016-09-08 9:08 Harry Pan
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