[PATCH v6 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing

[Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>]

These patches enable Intel Xeon Phi x200 feature to use MONITOR/MWAIT
instruction in ring 3 (userspace) Patches set MSR 0x140 for all logical CPUs.
Then expose it as CPU feature and introduces elf HWCAP capability for x86.
Reference:
https://software.intel.com/en-us/blogs/2016/10/06/intel-xeon-phi-product-family-x200-knl-user-mode-ring-3-monitor-and-mwait

v5:
When phir3mwait=disable is cmdline switch off r3 mwait feature
Fix typos

v4:
Wrapped the enabling code by CONFIG_X86_64
Add documentation for phir3mwait=disable cmdline switch
Move probe_ function call from early_intel_init to intel_init
Fixed commit messages

v3:
Included Daves and Thomas comments

v2:
Check MSR before wrmsrl
Shortened names
Used Word 3 for feature init_scattered_cpuid_features()
Fixed commit messages

Grzegorz Andrejczuk (4):
  x86/msr: Add R3MWAIT register and bit to msr-info.h
  x86: Add enabling of the R3MWAIT during boot
  x86: Use HWCAP2 to expose Xeon Phi ring 3 MWAIT
  x86/cpufeature: Add R3MWAIT to CPU features

 Documentation/kernel-parameters.txt |  5 +++++
 arch/x86/include/asm/cpufeatures.h  |  2 ++
 arch/x86/include/asm/elf.h          |  9 ++++++++
 arch/x86/include/asm/msr-index.h    |  5 +++++
 arch/x86/include/uapi/asm/hwcap2.h  |  7 +++++++
 arch/x86/kernel/cpu/common.c        |  3 +++
 arch/x86/kernel/cpu/intel.c         | 42 +++++++++++++++++++++++++++++++++++++
 7 files changed, 73 insertions(+)
 create mode 100644 arch/x86/include/uapi/asm/hwcap2.h

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2.5.1