From: Noam Camus <noamca@mellanox.com>
To: linux-snps-arc@lists.infradead.org
Cc: linux-kernel@vger.kernel.org, Elad Kanfi <eladkan@mellanox.com>,
Noam Camus <noamca@mellanox.com>
Subject: [PATCH v2 12/12] ARC: [plat-eznps] avoid toggling of DPC register
Date: Tue, 13 Jun 2017 17:03:56 +0300 [thread overview]
Message-ID: <1497362636-30353-13-git-send-email-noamca@mellanox.com> (raw)
In-Reply-To: <1497362636-30353-1-git-send-email-noamca@mellanox.com>
From: Elad Kanfi <eladkan@mellanox.com>
HW bug description: in case of HW thread context switch
the dpc configuration of the exiting thread is dragged
one cycle into the next thread.
In order to avoid the consequences of this bug, the DPC register
is set to an initial value, and not changed afterwards.
Signed-off-by: Elad Kanfi <eladkan@mellanox.com>
Signed-off-by: Noam Camus <noamca@mellanox.com>
---
arch/arc/plat-eznps/include/plat/ctop.h | 1 +
arch/arc/plat-eznps/mtm.c | 12 ++++++++++++
2 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/arch/arc/plat-eznps/include/plat/ctop.h b/arch/arc/plat-eznps/include/plat/ctop.h
index 7729d3d..0c7d110 100644
--- a/arch/arc/plat-eznps/include/plat/ctop.h
+++ b/arch/arc/plat-eznps/include/plat/ctop.h
@@ -39,6 +39,7 @@
#define CTOP_AUX_LOGIC_CORE_ID (CTOP_AUX_BASE + 0x018)
#define CTOP_AUX_MT_CTRL (CTOP_AUX_BASE + 0x020)
#define CTOP_AUX_HW_COMPLY (CTOP_AUX_BASE + 0x024)
+#define CTOP_AUX_DPC (CTOP_AUX_BASE + 0x02C)
#define CTOP_AUX_LPC (CTOP_AUX_BASE + 0x030)
#define CTOP_AUX_EFLAGS (CTOP_AUX_BASE + 0x080)
#define CTOP_AUX_IACK (CTOP_AUX_BASE + 0x088)
diff --git a/arch/arc/plat-eznps/mtm.c b/arch/arc/plat-eznps/mtm.c
index dd1ea1f..777231d 100644
--- a/arch/arc/plat-eznps/mtm.c
+++ b/arch/arc/plat-eznps/mtm.c
@@ -112,6 +112,18 @@ void mtm_enable_core(unsigned int cpu)
int i;
struct nps_host_reg_aux_mt_ctrl mt_ctrl;
struct nps_host_reg_mtm_cfg mtm_cfg;
+ struct nps_host_reg_aux_dpc dpc;
+
+ /*
+ * Initializing dpc register in each CPU.
+ * Overwriting the init value of the DPC
+ * register so that CMEM and FMT virtual address
+ * spaces are accessible, and Data Plane HW
+ * facilities are enabled.
+ */
+ dpc.ien = 1;
+ dpc.men = 1;
+ write_aux_reg(CTOP_AUX_DPC, dpc.value);
if (NPS_CPU_TO_THREAD_NUM(cpu) != 0)
return;
--
1.7.1
prev parent reply other threads:[~2017-06-13 14:04 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-06-13 14:03 [PATCH v2 00/12] plat-eznps upstream cont. set 2 Noam Camus
2017-06-13 14:03 ` [PATCH v2 01/12] ARC: [plat-eznps] Handle memory error as an exception Noam Camus
2017-06-14 22:39 ` Vineet Gupta
2017-06-13 14:03 ` [PATCH v2 02/12] ARC: set level of log per CPU during boot to be debug level Noam Camus
2017-06-14 22:45 ` Vineet Gupta
2017-06-13 14:03 ` [PATCH v2 03/12] ARC: send ipi to all cpus sharing task mm in case of page fault Noam Camus
2017-06-13 14:03 ` [PATCH v2 04/12] ARC: Allow irq threading Noam Camus
2017-06-13 14:03 ` [PATCH v2 05/12] ARC: Add CPU topology Noam Camus
2017-06-13 14:03 ` [PATCH v2 06/12] ARC: Support more than one PGDIR for KVADDR Noam Camus
2017-06-13 14:03 ` [PATCH v2 07/12] ARC: [NUMA] added CONFIG_NUMA for plat-eznps Noam Camus
2017-06-13 14:03 ` [PATCH v2 08/12] ARC: [plat-eznps] new command line argument for HW scheduler at MTM Noam Camus
2017-06-14 22:49 ` Vineet Gupta
2017-06-13 14:03 ` [PATCH v2 09/12] ARC: [plat-eznps] Update the init sequence of aux regs per cpu Noam Camus
2017-06-13 14:03 ` [PATCH v2 10/12] ARC: [plat-eznps] Save/Restore extra auxiliary registers Noam Camus
2017-06-13 14:03 ` [PATCH v2 11/12] ARC: [plat-eznps] handle dedicated AUX registers Noam Camus
2017-06-13 14:03 ` Noam Camus [this message]
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