From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
Michael Turquette <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@codeaurora.org>,
Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
<linux-clk@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<linux-kernel@vger.kernel.org>
Cc: Alex Frid <afrid@nvidia.com>
Subject: [PATCH 07/14] clk: tegra: Add TEGRA_PERIPH_ON_APB flag to I2C
Date: Tue, 25 Jul 2017 13:34:08 +0300 [thread overview]
Message-ID: <1500978856-5981-8-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1500978856-5981-1-git-send-email-pdeschrijver@nvidia.com>
From: Alex Frid <afrid@nvidia.com>
I2C controllers are also on the APB bus and therefor need this flag to handle
resets correctly.
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
drivers/clk/tegra/clk-tegra-periph.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/tegra/clk-tegra-periph.c b/drivers/clk/tegra/clk-tegra-periph.c
index 294bfe4..848255c 100644
--- a/drivers/clk/tegra/clk-tegra-periph.c
+++ b/drivers/clk/tegra/clk-tegra-periph.c
@@ -216,7 +216,8 @@
_clk_num, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, NULL, NULL, _parents, _offset,\
30, MASK(2), 0, 0, 16, 0, TEGRA_DIVIDER_ROUND_UP,\
- _clk_num, 0, _clk_id, _parents##_idx, 0, NULL)
+ _clk_num, TEGRA_PERIPH_ON_APB, _clk_id, \
+ _parents##_idx, 0, NULL)
#define XUSB(_name, _parents, _offset, \
_clk_num, _gate_flags, _clk_id) \
--
1.9.1
next prev parent reply other threads:[~2017-07-25 10:37 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-07-25 10:34 [PATCH 00/14] Fixes for Tegra clocks Peter De Schrijver
2017-07-25 10:34 ` [PATCH 01/14] clk: tegra: fix SS control on PLL enable/disable Peter De Schrijver
2017-07-25 10:34 ` [PATCH 02/14] clk: tegra: Enable PLL_SS for Tegra210 Peter De Schrijver
2017-07-25 10:34 ` [PATCH 03/14] clk: tegra: disable SSC for PLL_D2 Peter De Schrijver
2017-07-25 10:34 ` [PATCH 04/14] clk: tegra210: remove non-existing VFIR clock Peter De Schrijver
2017-07-25 10:34 ` [PATCH 05/14] clk: tegra: Init cfg structure in _get_pll_mnp Peter De Schrijver
2017-07-25 10:34 ` [PATCH 06/14] clk: tegra: Fix T210 effective NDIV calculation Peter De Schrijver
2017-07-25 10:34 ` Peter De Schrijver [this message]
2017-07-25 10:34 ` [PATCH 08/14] clk: tegra: change post IDDQ release delay to 5us Peter De Schrijver
2017-07-25 10:34 ` [PATCH 09/14] clk: tegra: don't warn for pll_d2 defaults unnecessarily Peter De Schrijver
2017-07-25 10:34 ` [PATCH 10/14] clk: tegra: Re-factor T210 PLLX registration Peter De Schrijver
2017-07-25 10:34 ` [PATCH 11/14] clk: tegra: Update T210 PLLSS (D2/DP) registration Peter De Schrijver
2017-07-25 10:34 ` [PATCH 12/14] clk: tegra: Fix T210 PLLRE registration Peter De Schrijver
2017-07-25 10:34 ` [PATCH 13/14] clk: tegra: Correct Tegra210 UTMIPLL poweron delay Peter De Schrijver
2017-07-25 10:34 ` [PATCH 14/14] clk: tegra: Fix Tegra210 PLLU initialization Peter De Schrijver
2017-07-26 1:37 ` [PATCH 00/14] Fixes for Tegra clocks Stephen Boyd
2017-07-26 8:27 ` Peter De Schrijver
2017-07-27 18:54 ` Stephen Boyd
2017-08-17 13:48 ` Thierry Reding
2017-08-23 23:07 ` Stephen Boyd
2017-08-17 13:31 ` Thierry Reding
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