From: Jerome Brunet <jbrunet@baylibre.com>
To: Yixun Lan <yixun.lan@amlogic.com>,
Linus Walleij <linus.walleij@linaro.org>,
Kevin Hilman <khilman@baylibre.com>
Cc: Neil Armstrong <narmstrong@baylibre.com>,
Carlo Caione <carlo@caione.org>,
Xingyu Chen <xingyu.chen@amlogic.com>,
linux-gpio@vger.kernel.org, linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/2] pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC
Date: Mon, 20 Nov 2017 11:33:11 +0100 [thread overview]
Message-ID: <1511173991.6971.7.camel@baylibre.com> (raw)
In-Reply-To: <20171120100825.16613-2-yixun.lan@amlogic.com>
On Mon, 2017-11-20 at 18:08 +0800, Yixun Lan wrote:
> From: Xingyu Chen <xingyu.chen@amlogic.com>
>
> The pin controller has been updated in the Amlogic Meson AXG series,
> which use continuous 4-bit register to select function for each pin.
> In order to support this, a new pinmux operations "meson_axg_pmx_ops"
> has been added.
>
> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
> Signed-off-by: Xingyu Chen <xingyu.chen@amlogic.com>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
next prev parent reply other threads:[~2017-11-20 10:33 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-11-20 10:08 [PATCH v2 0/2] add pinctrl driver " Yixun Lan
2017-11-20 10:08 ` [PATCH v2 1/2] pinctrl: meson-axg: Introduce a pinctrl pinmux ops " Yixun Lan
2017-11-20 10:33 ` Jerome Brunet [this message]
2017-11-30 13:29 ` Linus Walleij
2017-11-20 10:08 ` [PATCH v2 2/2] pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC Yixun Lan
2017-11-20 10:34 ` Jerome Brunet
2017-11-30 13:31 ` Linus Walleij
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