From: Sohil Mehta <sohil.mehta@intel.com>
To: Joerg Roedel <joro@8bytes.org>,
Alex Williamson <alex.williamson@redhat.com>
Cc: David Woodhouse <dwmw2@infradead.org>,
Ashok Raj <ashok.raj@intel.com>,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
Gayatri Kammela <gayatri.kammela@intel.com>,
Sohil Mehta <sohil.mehta@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Andy Shevchenko <andriy.shevchenko@intel.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
Fenghua Yu <fenghua.yu@intel.com>,
Kirill Shutemov <kirill.shutemov@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>
Subject: [PATCH 1/4] iommu/vt-d: Enable upto 57 bits of domain address width
Date: Wed, 20 Dec 2017 11:59:24 -0800 [thread overview]
Message-ID: <1513799967-22454-2-git-send-email-sohil.mehta@intel.com> (raw)
In-Reply-To: <1513799967-22454-1-git-send-email-sohil.mehta@intel.com>
Update the IOMMU default domain address width to 57 bits. This would
enable the IOMMU to do upto 5-levels of paging for second level
translations - IOVA translation requests without PASID.
Even though the maximum supported address width is being increased to
57, __iommu_calculate_agaw() would set the actual supported address
width to the maximum support available in IOMMU hardware.
Signed-off-by: Sohil Mehta <sohil.mehta@intel.com>
---
drivers/iommu/intel-iommu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index 4a2de34..457795b 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -64,7 +64,7 @@
#define IOAPIC_RANGE_END (0xfeefffff)
#define IOVA_START_ADDR (0x1000)
-#define DEFAULT_DOMAIN_ADDRESS_WIDTH 48
+#define DEFAULT_DOMAIN_ADDRESS_WIDTH 57
#define MAX_AGAW_WIDTH 64
#define MAX_AGAW_PFN_WIDTH (MAX_AGAW_WIDTH - VTD_PAGE_SHIFT)
--
2.7.4
next prev parent reply other threads:[~2017-12-20 19:59 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-20 19:59 [PATCH 0/4] Add support for Intel IOMMU 5-level paging Sohil Mehta
2017-12-20 19:59 ` Sohil Mehta [this message]
2017-12-20 19:59 ` [PATCH 2/4] iommu/vt-d: Add a check for 1GB page support Sohil Mehta
2017-12-20 19:59 ` [PATCH 3/4] iommu/vt-d: Add a check for 5-level paging support Sohil Mehta
2017-12-20 19:59 ` [PATCH 4/4] iommu/vt-d: Enable 5-level paging mode in the PASID entry Sohil Mehta
2018-01-17 14:03 ` [PATCH 0/4] Add support for Intel IOMMU 5-level paging Joerg Roedel
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