From: Joerg Roedel <joro@8bytes.org>
To: Sohil Mehta <sohil.mehta@intel.com>
Cc: Alex Williamson <alex.williamson@redhat.com>,
David Woodhouse <dwmw2@infradead.org>,
Ashok Raj <ashok.raj@intel.com>,
iommu@lists.linux-foundation.org, linux-kernel@vger.kernel.org,
Jacob Pan <jacob.jun.pan@linux.intel.com>,
Gayatri Kammela <gayatri.kammela@intel.com>,
Ravi V Shankar <ravi.v.shankar@intel.com>,
Andy Shevchenko <andriy.shevchenko@intel.com>,
Lu Baolu <baolu.lu@linux.intel.com>,
Fenghua Yu <fenghua.yu@intel.com>,
Kirill Shutemov <kirill.shutemov@linux.intel.com>,
Dave Hansen <dave.hansen@intel.com>
Subject: Re: [PATCH 0/4] Add support for Intel IOMMU 5-level paging
Date: Wed, 17 Jan 2018 15:03:24 +0100 [thread overview]
Message-ID: <20180117140324.6wkbi2bbt6xug53d@8bytes.org> (raw)
In-Reply-To: <1513799967-22454-1-git-send-email-sohil.mehta@intel.com>
On Wed, Dec 20, 2017 at 11:59:23AM -0800, Sohil Mehta wrote:
> Sohil Mehta (4):
> iommu/vt-d: Enable upto 57 bits of domain address width
> iommu/vt-d: Add a check for 1GB page support
> iommu/vt-d: Add a check for 5-level paging support
> iommu/vt-d: Enable 5-level paging mode in the PASID entry
>
> drivers/iommu/intel-iommu.c | 2 +-
> drivers/iommu/intel-svm.c | 23 +++++++++++++++++++++--
> include/linux/intel-iommu.h | 2 ++
> 3 files changed, 24 insertions(+), 3 deletions(-)
Applied, thanks.
prev parent reply other threads:[~2018-01-17 14:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-12-20 19:59 Sohil Mehta
2017-12-20 19:59 ` [PATCH 1/4] iommu/vt-d: Enable upto 57 bits of domain address width Sohil Mehta
2017-12-20 19:59 ` [PATCH 2/4] iommu/vt-d: Add a check for 1GB page support Sohil Mehta
2017-12-20 19:59 ` [PATCH 3/4] iommu/vt-d: Add a check for 5-level paging support Sohil Mehta
2017-12-20 19:59 ` [PATCH 4/4] iommu/vt-d: Enable 5-level paging mode in the PASID entry Sohil Mehta
2018-01-17 14:03 ` Joerg Roedel [this message]
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