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From: Matt Redfearn <matt.redfearn@mips.com>
To: Ralf Baechle <ralf@linux-mips.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-mips@linux-mips.org>,
	Matt Redfearn <matt.redfearn@mips.com>,
	<linux-kernel@vger.kernel.org>,
	Philippe Ombredanne <pombredanne@nexb.com>,
	Kate Stewart <kstewart@linuxfoundation.org>,
	Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Subject: [PATCH 1/6] MIPS: Move ehb() to barrier.h
Date: Fri, 5 Jan 2018 10:31:05 +0000	[thread overview]
Message-ID: <1515148270-9391-2-git-send-email-matt.redfearn@mips.com> (raw)
In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com>

The current location of ehb() in mipsmtregs.h does not make sense, since
it is not strictly related to multi-threading, and may be used in code
which does not include mipsmtregs.h

Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
---

 arch/mips/include/asm/barrier.h    | 13 +++++++++++++
 arch/mips/include/asm/mipsmtregs.h |  8 --------
 2 files changed, 13 insertions(+), 8 deletions(-)

diff --git a/arch/mips/include/asm/barrier.h b/arch/mips/include/asm/barrier.h
index a5eb1bb199a7..a98fd8a2bba2 100644
--- a/arch/mips/include/asm/barrier.h
+++ b/arch/mips/include/asm/barrier.h
@@ -222,6 +222,19 @@
 #define __smp_mb__before_atomic()	__smp_mb__before_llsc()
 #define __smp_mb__after_atomic()	smp_llsc_mb()
 
+/**
+ * ehb() - Execution Hazard Barrier
+ *
+ * Stop instruction execution until execution hazards are cleared
+ */
+static inline void ehb(void)
+{
+	__asm__ __volatile__(
+	"	.set	mips32r2				\n"
+	"	ehb						\n"
+	"	.set	mips0					\n");
+}
+
 #include <asm-generic/barrier.h>
 
 #endif /* __ASM_BARRIER_H */
diff --git a/arch/mips/include/asm/mipsmtregs.h b/arch/mips/include/asm/mipsmtregs.h
index 212336b7c0f4..4acfc78bc504 100644
--- a/arch/mips/include/asm/mipsmtregs.h
+++ b/arch/mips/include/asm/mipsmtregs.h
@@ -274,14 +274,6 @@ static inline void emt(int previous)
 		__raw_emt();
 }
 
-static inline void ehb(void)
-{
-	__asm__ __volatile__(
-	"	.set	mips32r2				\n"
-	"	ehb						\n"
-	"	.set	mips0					\n");
-}
-
 #define mftc0(rt,sel)							\
 ({									\
 	 unsigned long	__res;						\
-- 
2.7.4

  reply	other threads:[~2018-01-05 10:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-05 10:31 [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Matt Redfearn
2018-01-05 10:31 ` Matt Redfearn [this message]
2018-05-17 14:30   ` [PATCH 1/6] MIPS: Move ehb() to barrier.h James Hogan
2018-01-05 10:31 ` [PATCH 2/6] MIPS: CPS: Introduce mips_gic_enable_eic Matt Redfearn
2018-01-05 10:31 ` [PATCH 3/6] MIPS: Generic: Support GIC in EIC mode Matt Redfearn
2018-02-05 14:11   ` James Hogan
2018-01-05 10:31 ` [PATCH 4/6] irqchip/mips-gic: Always attempt to enable " Matt Redfearn
2018-01-05 10:31 ` [PATCH 5/6] irqchip/mips-gic: Use separate vector for shared interrupts in " Matt Redfearn
2018-01-05 10:31 ` [PATCH 6/6] irqchip/mips-gic: Separate local interrupt handling Matt Redfearn
2018-03-14 11:15 ` [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Marc Zyngier
2018-03-14 15:46   ` James Hogan
2018-03-14 15:53     ` Marc Zyngier

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