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From: Matt Redfearn <matt.redfearn@mips.com>
To: Ralf Baechle <ralf@linux-mips.org>, Thomas Gleixner <tglx@linutronix.de>
Cc: <linux-mips@linux-mips.org>,
	Matt Redfearn <matt.redfearn@mips.com>,
	Paul Burton <paul.burton@mips.com>,
	<linux-kernel@vger.kernel.org>
Subject: [PATCH 3/6] MIPS: Generic: Support GIC in EIC mode
Date: Fri, 5 Jan 2018 10:31:07 +0000	[thread overview]
Message-ID: <1515148270-9391-4-git-send-email-matt.redfearn@mips.com> (raw)
In-Reply-To: <1515148270-9391-1-git-send-email-matt.redfearn@mips.com>

The GIC supports running in External Interrupt Controller (EIC) mode,
and will signal this via cpu_has_veic if enabled in hardware. Currently
the generic kernel will panic if cpu_has_veic is set - but the GIC can
legitimately set this flag if either configured to boot in EIC mode, or
if the GIC driver enables this mode. Make the kernel not panic in this
case, and instead just check if the GIC is present. If so, use it's CPU
local interrupt routing functions. If an EIC is present, but it is not
the GIC, then the kernel does not know how to get the VIRQ for the CPU
local interrupts and should panic. Support for alternative EICs being
present is needed here for the generic kernel to support them.

Suggested-by: Paul Burton <paul.burton@mips.com>
Signed-off-by: Matt Redfearn <matt.redfearn@mips.com>
---

 arch/mips/generic/irq.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/arch/mips/generic/irq.c b/arch/mips/generic/irq.c
index 394f8161e462..cb7fdaeef426 100644
--- a/arch/mips/generic/irq.c
+++ b/arch/mips/generic/irq.c
@@ -22,10 +22,10 @@ int get_c0_fdc_int(void)
 {
 	int mips_cpu_fdc_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_fdc_irq = gic_get_c0_fdc_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else if (cp0_fdc_irq >= 0)
 		mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq;
 	else
@@ -38,10 +38,10 @@ int get_c0_perfcount_int(void)
 {
 	int mips_cpu_perf_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_perf_irq = gic_get_c0_perfcount_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else if (cp0_perfcount_irq >= 0)
 		mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
 	else
@@ -54,10 +54,10 @@ unsigned int get_c0_compare_int(void)
 {
 	int mips_cpu_timer_irq;
 
-	if (cpu_has_veic)
-		panic("Unimplemented!");
-	else if (mips_gic_present())
+	if (mips_gic_present())
 		mips_cpu_timer_irq = gic_get_c0_compare_int();
+	else if (cpu_has_veic)
+		panic("Unimplemented!");
 	else
 		mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
 
-- 
2.7.4

  parent reply	other threads:[~2018-01-05 10:32 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-01-05 10:31 [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Matt Redfearn
2018-01-05 10:31 ` [PATCH 1/6] MIPS: Move ehb() to barrier.h Matt Redfearn
2018-05-17 14:30   ` James Hogan
2018-01-05 10:31 ` [PATCH 2/6] MIPS: CPS: Introduce mips_gic_enable_eic Matt Redfearn
2018-01-05 10:31 ` Matt Redfearn [this message]
2018-02-05 14:11   ` [PATCH 3/6] MIPS: Generic: Support GIC in EIC mode James Hogan
2018-01-05 10:31 ` [PATCH 4/6] irqchip/mips-gic: Always attempt to enable " Matt Redfearn
2018-01-05 10:31 ` [PATCH 5/6] irqchip/mips-gic: Use separate vector for shared interrupts in " Matt Redfearn
2018-01-05 10:31 ` [PATCH 6/6] irqchip/mips-gic: Separate local interrupt handling Matt Redfearn
2018-03-14 11:15 ` [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available Marc Zyngier
2018-03-14 15:46   ` James Hogan
2018-03-14 15:53     ` Marc Zyngier

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