From: Peter De Schrijver <pdeschrijver@nvidia.com>
To: <linux-tegra@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<mturquette@baylibre.com>, <sboyd@codeaurora.org>,
<robh+dt@kernel.org>, <mark.rutland@arm.com>,
<devicetree@vger.kernel.org>, <lgirdwood@gmail.com>,
<broonie@kernel.org>, <linux-kernel@vger.kernel.org>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Subject: [PATCH v3 11/11] arm64: dts: nvidia: Tegra210 CPU clock definition
Date: Tue, 6 Feb 2018 18:34:12 +0200 [thread overview]
Message-ID: <1517934852-23255-12-git-send-email-pdeschrijver@nvidia.com> (raw)
In-Reply-To: <1517934852-23255-1-git-send-email-pdeschrijver@nvidia.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
---
arch/arm64/boot/dts/nvidia/tegra210.dtsi | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra210.dtsi b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
index bc9851a..a7fddae 100644
--- a/arch/arm64/boot/dts/nvidia/tegra210.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra210.dtsi
@@ -1229,6 +1229,13 @@
device_type = "cpu";
compatible = "arm,cortex-a57";
reg = <0>;
+ clocks = <&tegra_car TEGRA210_CLK_CCLK_G>,
+ <&tegra_car TEGRA210_CLK_PLL_X>,
+ <&tegra_car TEGRA210_CLK_PLL_P_OUT_CPU>,
+ <&dfll>;
+ clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
+ /* FIXME: what's the actual transition time? */
+ clock-latency = <300000>;
};
cpu@1 {
--
1.9.1
prev parent reply other threads:[~2018-02-06 16:36 UTC|newest]
Thread overview: 45+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-02-06 16:34 [PATCH v3 00/11] Tegra210 DFLL implementation Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 01/11] regulator: core: add API to get voltage constraints Peter De Schrijver
2018-02-06 16:35 ` Mark Brown
2018-02-07 8:47 ` Peter De Schrijver
2018-02-07 10:43 ` Mark Brown
2018-02-07 12:37 ` Peter De Schrijver
2018-02-07 14:18 ` Mark Brown
2018-02-07 14:32 ` Peter De Schrijver
2018-02-07 15:01 ` Mark Brown
2018-02-07 15:20 ` Peter De Schrijver
2018-02-07 15:37 ` Mark Brown
2018-02-08 10:04 ` Laxman Dewangan
2018-02-08 14:58 ` Mark Brown
2018-02-06 16:34 ` [PATCH v3 02/11] clk: tegra: retrieve regulator info from framework Peter De Schrijver
2018-03-08 22:26 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 03/11] clk: tegra: dfll registration for multiple SoCs Peter De Schrijver
2018-03-08 22:15 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 04/11] clk: tegra: add CVB tables for Tegra210 CPU DFLL Peter De Schrijver
2018-03-08 22:28 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 05/11] clk: tegra: prepare dfll driver for PWM regulator Peter De Schrijver
2018-03-08 22:50 ` Jon Hunter
2018-03-12 9:14 ` Peter De Schrijver
2018-03-12 11:08 ` Jon Hunter
2018-03-13 9:03 ` Peter De Schrijver
2018-03-13 10:07 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 06/11] clk: tegra: dfll: support PWM regulator control Peter De Schrijver
2018-03-08 23:15 ` Jon Hunter
2018-03-09 8:12 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 07/11] dt-bindings: tegra: Update DFLL binding for PWM regulator Peter De Schrijver
2018-02-09 23:19 ` Rob Herring
2018-03-08 23:21 ` Jon Hunter
2018-03-12 9:10 ` Peter De Schrijver
2018-02-06 16:34 ` [PATCH v3 08/11] clk: tegra: build clk-dfll.c for Tegra124 and Tegra210 Peter De Schrijver
2018-03-08 23:22 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 09/11] cpufreq: tegra124-cpufreq: extend to support Tegra210 Peter De Schrijver
2018-03-08 23:25 ` Jon Hunter
2018-03-09 8:14 ` Peter De Schrijver
2018-03-12 10:14 ` Jon Hunter
2018-03-13 9:28 ` Peter De Schrijver
2018-03-09 9:11 ` Viresh Kumar
2018-03-12 12:15 ` Jon Hunter
2018-03-13 9:51 ` Peter De Schrijver
2018-03-13 10:20 ` Jon Hunter
2018-02-06 16:34 ` [PATCH v3 10/11] arm64: dts: tegra: Add Tegra210 DFLL definition Peter De Schrijver
2018-02-06 16:34 ` Peter De Schrijver [this message]
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