Re: [PATCH] arm64: dts: qcom: sm8750: Add camera clock controller

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 12/6/25 4:45 AM, Dmitry Baryshkov wrote:
> On Wed, Dec 03, 2025 at 04:03:26PM +0200, Vladimir Zapolskiy wrote:
>> Hi Taniya.
>>
>> On 12/3/25 12:32, Taniya Das wrote:
>>> Add the camcc clock controller device node for SM8750 SoC.
>>>
>>> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
>>> ---
>>>   arch/arm64/boot/dts/qcom/sm8750.dtsi | 35 ++++++++++++++++++++++++++++++++++-
>>>   1 file changed, 34 insertions(+), 1 deletion(-)
> 
>>> @@ -2046,6 +2047,22 @@ aggre2_noc: interconnect@1700000 {
>>>   			clocks = <&rpmhcc RPMH_IPA_CLK>;
>>>   		};
>>> +		cambistmclkcc: clock-controller@1760000 {
>>> +		       compatible = "qcom,sm8750-cambistmclkcc";
>>> +		       reg = <0x0 0x1760000 0x0 0x6000>;
>>> +		       clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK> ,
>>> +				<&bi_tcxo_div2>,
>>> +				<&bi_tcxo_ao_div2>,
>>> +				<&sleep_clk>;
>>> +			power-domains = <&rpmhpd RPMHPD_MMCX>,
>>> +					<&rpmhpd RPMHPD_MX>;
>>> +			required-opps = <&rpmhpd_opp_low_svs>,
>>> +					<&rpmhpd_opp_low_svs>;
>>> +			#clock-cells = <1>;
>>> +			#reset-cells = <1>;
>>> +			#power-domain-cells = <1>;
>>
>> I've briefly checked the recently sent driver, and I didn't find that this
>> clock controller serves as a reset controller or a power domain controller.
>>
>> And if so, these properties shall be obviously removed.
> 
> I'd agree here.

This block is most definitely a reset provider, but none are described
in Linux as of right now

I don't see any GDSCs though

Konrad