[PATCH] clk: divider: Use round off divisor instead of round up

[Tejas Patel <tejas.patel@xilinx.com>]

divider_get_val() is used to find clock divisor which is
giving round up value. So even though actual divisor is closer to
round down integer value it will return round up integer value.
This can result into large variation between expected clock rate and
actual clock rate.

See for example:
Parent rate is 1400MHz and desired child rate is 693MHz.
So if we calculate simple divisor for child clock it would be
1400000000/693000000 = 2.02. But, because of roundup logic
(DIV_ROUND_UP_ULL(1400000000, 693000000)) divisor returned from
divider_get_val() will be 3.

So actual child rate would be (1400000000/3) = 466666667 instead of
693000000. Here, difference between expected child rate and actual child
rate is approx 226MHz. So there is almost 32% error between desired and
actual clock rate.

Fix this by using round off value (DIV_ROUND_CLOSEST_ULL) instead of
round up/down.

Signed-off-by: Tejas Patel <tejas.patel@xilinx.com>
---
 drivers/clk/clk-divider.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index b6234a5..6ae6d43 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -391,7 +391,7 @@ int divider_get_val(unsigned long rate, unsigned long parent_rate,
 {
        unsigned int div, value;

-       div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
+       div = DIV_ROUND_CLOSEST_ULL((u64)parent_rate, rate);

        if (!_is_valid_div(table, div, flags))
                return -EINVAL;
--
2.7.4

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