[PATCH 1/2] arm64: dts: tegra186: Add dma-ranges to avoid using bounce buffers

[PATCH 1/2] arm64: dts: tegra186: Add dma-ranges to avoid using bounce buffers

[Krishna Reddy]

Add dma-ranges to avoid using DMA bounce buffers unnecessarily for
the devices that can address the physcial memory and don't
have SMMU enabled.

This also resolves the failures in attaching devices to IOMMU.
The following error is caused by the check in io-pgtable-arm.c, where
the dma address is expected to match the physical address for the IOMMU
devices that don't support coherent page table walking. Bounce buffer
usage is causing the mismatch and device add failure.

[    7.000461] arm-smmu 12000000.iommu: Cannot accommodate DMA
translation for IOMMU page tables
[    7.010513] iommu: Failed to add device 15200000.display to group 0:
-12

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 2f3c8e2..230c0c8 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -14,6 +14,7 @@
 	interrupt-parent = <&gic>;
 	#address-cells = <2>;
 	#size-cells = <2>;
+	dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
 
 	misc@100000 {
 		compatible = "nvidia,tegra186-misc";
-- 
2.1.4

[PATCH 2/2] arm64: dts: tegra186: Enable IOMMU for SDHCI

[Krishna Reddy]

Enable IOMMU for all SDHCI controllers in Tegra186.

Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
---
 arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 230c0c8..996997e 100644
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -234,6 +234,7 @@
 		compatible = "nvidia,tegra186-sdhci";
 		reg = <0x0 0x03400000 0x0 0x10000>;
 		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu TEGRA186_SID_SDMMC1>;
 		clocks = <&bpmp TEGRA186_CLK_SDMMC1>;
 		clock-names = "sdhci";
 		resets = <&bpmp TEGRA186_RESET_SDMMC1>;
@@ -259,6 +260,7 @@
 		compatible = "nvidia,tegra186-sdhci";
 		reg = <0x0 0x03420000 0x0 0x10000>;
 		interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu TEGRA186_SID_SDMMC2>;
 		clocks = <&bpmp TEGRA186_CLK_SDMMC2>;
 		clock-names = "sdhci";
 		resets = <&bpmp TEGRA186_RESET_SDMMC2>;
@@ -279,6 +281,7 @@
 		compatible = "nvidia,tegra186-sdhci";
 		reg = <0x0 0x03440000 0x0 0x10000>;
 		interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu TEGRA186_SID_SDMMC3>;
 		clocks = <&bpmp TEGRA186_CLK_SDMMC3>;
 		clock-names = "sdhci";
 		resets = <&bpmp TEGRA186_RESET_SDMMC3>;
@@ -301,6 +304,7 @@
 		compatible = "nvidia,tegra186-sdhci";
 		reg = <0x0 0x03460000 0x0 0x10000>;
 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
+		iommus = <&smmu TEGRA186_SID_SDMMC4>;
 		clocks = <&bpmp TEGRA186_CLK_SDMMC4>;
 		clock-names = "sdhci";
 		assigned-clocks = <&bpmp TEGRA186_CLK_SDMMC4>,
-- 
2.1.4