From: "Mehta, Sanju" <Sanju.Mehta@amd.com>
To: "S-k, Shyam-sundar" <Shyam-sundar.S-k@amd.com>,
"jdmason@kudzu.us" <jdmason@kudzu.us>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"allenbh@gmail.com" <allenbh@gmail.com>
Cc: "linux-ntb@googlegroups.com" <linux-ntb@googlegroups.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"Mehta, Sanju" <Sanju.Mehta@amd.com>
Subject: [PATCH 4/4] NTB: ntb_hw_amd: set peer limit register
Date: Fri, 15 Feb 2019 09:21:46 +0000 [thread overview]
Message-ID: <1550222486-30144-1-git-send-email-Sanju.Mehta@amd.com> (raw)
From: Sanjay R Mehta <sanju.mehta@amd.com>
As per amd ntb spec it says that peer limit register
must be programmed
Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com>
---
drivers/ntb/hw/amd/ntb_hw_amd.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
index efb214f..cd463e1 100644
--- a/drivers/ntb/hw/amd/ntb_hw_amd.c
+++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
@@ -160,8 +160,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
}
/* set and verify setting the limit */
- write64(limit, mmio + limit_reg);
- reg_val = read64(mmio + limit_reg);
+ write64(limit, peer_mmio + limit_reg);
+ reg_val = read64(peer_mmio + limit_reg);
if (reg_val != limit) {
write64(base_addr, mmio + limit_reg);
write64(0, peer_mmio + xlat_reg);
@@ -183,8 +183,8 @@ static int amd_ntb_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
}
/* set and verify setting the limit */
- writel(limit, mmio + limit_reg);
- reg_val = readl(mmio + limit_reg);
+ writel(limit, peer_mmio + limit_reg);
+ reg_val = readl(peer_mmio + limit_reg);
if (reg_val != limit) {
writel(base_addr, mmio + limit_reg);
writel(0, peer_mmio + xlat_reg);
--
2.7.4
reply other threads:[~2019-02-15 9:22 UTC|newest]
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