* [PATCH 0/2] Add EDMA0/EDMA1 nodes @ 2019-03-26 9:42 Daniel Baluta 2019-03-26 9:43 ` [PATCH 1/2] bindings: fsl-edma: Document fsl,imx8qm-edma compatbile string Daniel Baluta 2019-03-26 9:43 ` [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes Daniel Baluta 0 siblings, 2 replies; 7+ messages in thread From: Daniel Baluta @ 2019-03-26 9:42 UTC (permalink / raw) To: shawnguo Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, dl-linux-imx, Aisheng Dong, Peng Fan, Anson Huang, devicetree, linux-arm-kernel, S.j. Wang, linux-kernel, Teo Hall, Daniel Baluta First patch documents the fsl,imx8qm-edma string while the second adds the two EDMA nodes used by Audio peripherals. Daniel Baluta (2): bindings: fsl-edma: Document fsl,imx8qm-edma compatbile string arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes .../devicetree/bindings/dma/fsl-edma.txt | 1 + arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 72 +++++++++++++++++++ 2 files changed, 73 insertions(+) -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 1/2] bindings: fsl-edma: Document fsl,imx8qm-edma compatbile string 2019-03-26 9:42 [PATCH 0/2] Add EDMA0/EDMA1 nodes Daniel Baluta @ 2019-03-26 9:43 ` Daniel Baluta 2019-03-26 9:43 ` [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes Daniel Baluta 1 sibling, 0 replies; 7+ messages in thread From: Daniel Baluta @ 2019-03-26 9:43 UTC (permalink / raw) To: shawnguo Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, dl-linux-imx, Aisheng Dong, Peng Fan, Anson Huang, devicetree, linux-arm-kernel, S.j. Wang, linux-kernel, Teo Hall, Daniel Baluta Add imx8qm edma support. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> --- Documentation/devicetree/bindings/dma/fsl-edma.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/fsl-edma.txt b/Documentation/devicetree/bindings/dma/fsl-edma.txt index 97e213e07660..5294ee094313 100644 --- a/Documentation/devicetree/bindings/dma/fsl-edma.txt +++ b/Documentation/devicetree/bindings/dma/fsl-edma.txt @@ -9,6 +9,7 @@ group, DMAMUX0 or DMAMUX1, but not both. Required properties: - compatible : - "fsl,vf610-edma" for eDMA used similar to that on Vybrid vf610 SoC + - "fsl,imx8qm-edma" for eDMA used similar to that on i.MX8 SoC - reg : Specifies base physical address(s) and size of the eDMA registers. The 1st region is eDMA control register's address and size. The 2nd and the 3rd regions are programmable channel multiplexing -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes 2019-03-26 9:42 [PATCH 0/2] Add EDMA0/EDMA1 nodes Daniel Baluta 2019-03-26 9:43 ` [PATCH 1/2] bindings: fsl-edma: Document fsl,imx8qm-edma compatbile string Daniel Baluta @ 2019-03-26 9:43 ` Daniel Baluta 2019-03-26 13:30 ` Aisheng Dong 1 sibling, 1 reply; 7+ messages in thread From: Daniel Baluta @ 2019-03-26 9:43 UTC (permalink / raw) To: shawnguo Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, dl-linux-imx, Aisheng Dong, Peng Fan, Anson Huang, devicetree, linux-arm-kernel, S.j. Wang, linux-kernel, Teo Hall, Daniel Baluta i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily for audio components and the other two are for non-audio periperhals. This patch adds the EDMA0/EDMA1 nodes used by audio peripherals. EDMA0 contains channels for: * ASRC0 * ESAI0 * SPDIF0 * SAI0, SAI1, SAI2, SAI3 EDMA1 contains channels for: * ASRC1 * SAI4, SAI5 See chapter Audio DMA Memory Maps (2.2.3) from i.MX8QXP RM [1] This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP internal tree. [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf Cc: Teo Hall <teo.hall@nxp.com> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> --- arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 72 ++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index 0cb939861a60..9e959deb2499 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -182,6 +182,78 @@ #clock-cells = <1>; }; + edma0: dma-controller@591f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x59200000 0x10000>, /* asrc0 pair A input req */ + <0x59210000 0x10000>, /* asrc0 pair B input req */ + <0x59220000 0x10000>, /* asrc0 pair C input req */ + <0x59230000 0x10000>, /* asrc0 pair A output req */ + <0x59240000 0x10000>, /* asrc0 pair B output req */ + <0x59250000 0x10000>, /* asrc0 pair C output req */ + <0x59260000 0x10000>, /* esai0 rx */ + <0x59270000 0x10000>, /* esai0 tx */ + <0x59280000 0x10000>, /* spdif0 rx */ + <0x59290000 0x10000>, /* spdif0 tx */ + <0x592c0000 0x10000>, /* sai0 rx */ + <0x592d0000 0x10000>, /* sai0 tx */ + <0x592e0000 0x10000>, /* sai1 rx */ + <0x592f0000 0x10000>, /* sai1 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <14>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* asrc0 */ + "edma0-chan2-rx", "edma0-chan3-tx", + "edma0-chan4-tx", "edma0-chan5-tx", + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ + }; + + edma1: dma-controller@599F0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ + <0x0 0x59A10000 0x0 0x10000>, + <0x0 0x59A20000 0x0 0x10000>, + <0x0 0x59A30000 0x0 0x10000>, + <0x0 0x59A40000 0x0 0x10000>, + <0x0 0x59A50000 0x0 0x10000>, + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ + #dma-cells = <3>; + shared-interrupt; + dma-channels = <9>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* asrc1 */ + "edma1-chan2-rx", "edma1-chan3-tx", + "edma1-chan4-tx", "edma1-chan5-tx", + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ + "edma1-chan10-tx"; /* sai5 */ + }; + adma_lpuart0: serial@5a060000 { compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x5a060000 0x1000>; -- 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* RE: [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes 2019-03-26 9:43 ` [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes Daniel Baluta @ 2019-03-26 13:30 ` Aisheng Dong 2019-03-27 8:51 ` Daniel Baluta 0 siblings, 1 reply; 7+ messages in thread From: Aisheng Dong @ 2019-03-26 13:30 UTC (permalink / raw) To: Daniel Baluta, shawnguo Cc: robh+dt, mark.rutland, s.hauer, kernel, festevam, dl-linux-imx, Peng Fan, Anson Huang, devicetree, linux-arm-kernel, S.j. Wang, linux-kernel, Teo Hall > From: Daniel Baluta > Sent: Tuesday, March 26, 2019 5:43 PM > > i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily > for audio components and the other two are for non-audio periperhals. > > This patch adds the EDMA0/EDMA1 nodes used by audio peripherals. > > EDMA0 contains channels for: > * ASRC0 > * ESAI0 > * SPDIF0 > * SAI0, SAI1, SAI2, SAI3 > > EDMA1 contains channels for: > * ASRC1 > * SAI4, SAI5 > > See chapter Audio DMA Memory Maps (2.2.3) from i.MX8QXP RM [1] > > This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP > internal tree. > > [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf > > Cc: Teo Hall <teo.hall@nxp.com> > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> > --- > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 72 > ++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > index 0cb939861a60..9e959deb2499 100644 > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > @@ -182,6 +182,78 @@ > #clock-cells = <1>; > }; > > + edma0: dma-controller@591f0000 { > + compatible = "fsl,imx8qm-edma"; Should this be "fsl,imx8qxp-edma"? or "fsl,imx8qxp-edma", "fsl,imx8qm-edma"? Regards Dong Aisheng > + reg = <0x59200000 0x10000>, /* asrc0 pair A input req */ > + <0x59210000 0x10000>, /* asrc0 pair B input req */ > + <0x59220000 0x10000>, /* asrc0 pair C input req */ > + <0x59230000 0x10000>, /* asrc0 pair A output req */ > + <0x59240000 0x10000>, /* asrc0 pair B output req */ > + <0x59250000 0x10000>, /* asrc0 pair C output req */ > + <0x59260000 0x10000>, /* esai0 rx */ > + <0x59270000 0x10000>, /* esai0 tx */ > + <0x59280000 0x10000>, /* spdif0 rx */ > + <0x59290000 0x10000>, /* spdif0 tx */ > + <0x592c0000 0x10000>, /* sai0 rx */ > + <0x592d0000 0x10000>, /* sai0 tx */ > + <0x592e0000 0x10000>, /* sai1 rx */ > + <0x592f0000 0x10000>, /* sai1 tx */ > + #dma-cells = <3>; > + shared-interrupt; > + dma-channels = <14>; > + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc 0 > */ > + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ > + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */ > + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ > + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */ > + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, > + interrupt-names = "edma0-chan0-rx", "edma0-chan1-rx", /* > asrc0 */ > + "edma0-chan2-rx", "edma0-chan3-tx", > + "edma0-chan4-tx", "edma0-chan5-tx", > + "edma0-chan6-rx", "edma0-chan7-tx", /* esai0 */ > + "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */ > + "edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */ > + "edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */ > + }; > + > + edma1: dma-controller@599F0000 { > + compatible = "fsl,imx8qm-edma"; > + reg = <0x0 0x59A00000 0x0 0x10000>, /* asrc1 */ > + <0x0 0x59A10000 0x0 0x10000>, > + <0x0 0x59A20000 0x0 0x10000>, > + <0x0 0x59A30000 0x0 0x10000>, > + <0x0 0x59A40000 0x0 0x10000>, > + <0x0 0x59A50000 0x0 0x10000>, > + <0x0 0x59A80000 0x0 0x10000>, /* sai4 rx */ > + <0x0 0x59A90000 0x0 0x10000>, /* sai4 tx */ > + <0x0 0x59AA0000 0x0 0x10000>; /* sai5 tx */ > + #dma-cells = <3>; > + shared-interrupt; > + dma-channels = <9>; > + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* asrc 1 */ > + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ > + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ > + interrupt-names = "edma1-chan0-rx", "edma1-chan1-rx", /* > asrc1 */ > + "edma1-chan2-rx", "edma1-chan3-tx", > + "edma1-chan4-tx", "edma1-chan5-tx", > + "edma1-chan8-rx", "edma1-chan9-tx", /* sai4 */ > + "edma1-chan10-tx"; /* sai5 */ > + }; > + > adma_lpuart0: serial@5a060000 { > compatible = "fsl,imx8qxp-lpuart", "fsl,imx7ulp-lpuart"; > reg = <0x5a060000 0x1000>; > -- > 2.17.1 ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes 2019-03-26 13:30 ` Aisheng Dong @ 2019-03-27 8:51 ` Daniel Baluta 2019-03-27 9:33 ` Lucas Stach 0 siblings, 1 reply; 7+ messages in thread From: Daniel Baluta @ 2019-03-27 8:51 UTC (permalink / raw) To: Aisheng Dong Cc: Daniel Baluta, shawnguo, robh+dt, mark.rutland, s.hauer, kernel, festevam, dl-linux-imx, Peng Fan, Anson Huang, devicetree, linux-arm-kernel, S.j. Wang, linux-kernel, Teo Hall On Tue, Mar 26, 2019 at 3:31 PM Aisheng Dong <aisheng.dong@nxp.com> wrote: > > > From: Daniel Baluta > > Sent: Tuesday, March 26, 2019 5:43 PM > > > > i.MX8QXP contains a total of 4 EDMA controllers of which two are primarily > > for audio components and the other two are for non-audio periperhals. > > > > This patch adds the EDMA0/EDMA1 nodes used by audio peripherals. > > > > EDMA0 contains channels for: > > * ASRC0 > > * ESAI0 > > * SPDIF0 > > * SAI0, SAI1, SAI2, SAI3 > > > > EDMA1 contains channels for: > > * ASRC1 > > * SAI4, SAI5 > > > > See chapter Audio DMA Memory Maps (2.2.3) from i.MX8QXP RM [1] > > > > This patch is based on the dtsi file initially submitted by Teo Hall in i.MX NXP > > internal tree. > > > > [1] https://www.nxp.com/docs/en/reference-manual/IMX8DQXPRM.pdf > > > > Cc: Teo Hall <teo.hall@nxp.com> > > Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> > > --- > > arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 72 > > ++++++++++++++++++++++ > > 1 file changed, 72 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > index 0cb939861a60..9e959deb2499 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi > > @@ -182,6 +182,78 @@ > > #clock-cells = <1>; > > }; > > > > + edma0: dma-controller@591f0000 { > > + compatible = "fsl,imx8qm-edma"; Thanks for the comment Aisheng! > > Should this be "fsl,imx8qxp-edma"? Yes, I think that's the more clear approach although in our internal tree the edma driver uses only the "fsl,imx8qm-edma compatible. I will go with your suggestion. > or > "fsl,imx8qxp-edma", "fsl,imx8qm-edma"? One thing that it is not clear for me is why there are places where we use two compatible strings? I understand the situation where are two distinct drivers, but is there any other reason to add multiple compatible strings for a node in dts? thanks, Daniel. ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes 2019-03-27 8:51 ` Daniel Baluta @ 2019-03-27 9:33 ` Lucas Stach 2019-03-27 16:36 ` Daniel Baluta 0 siblings, 1 reply; 7+ messages in thread From: Lucas Stach @ 2019-03-27 9:33 UTC (permalink / raw) To: Daniel Baluta, Aisheng Dong Cc: mark.rutland, devicetree, Peng Fan, festevam, Anson Huang, Teo Hall, Daniel Baluta, s.hauer, linux-kernel, robh+dt, dl-linux-imx, kernel, shawnguo, S.j. Wang, linux-arm-kernel Hi Daniel, Am Mittwoch, den 27.03.2019, 10:51 +0200 schrieb Daniel Baluta: [...] > > > or > > "fsl,imx8qxp-edma", "fsl,imx8qm-edma"? > > One thing that it is not clear for me is why there are places > where we use two compatible strings? > > I understand the situation where are two distinct drivers, but is there > any other reason to add multiple compatible strings for a node in dts? We use 2 compatible string where there should not be any differences between the IP blocks of this SoC and a version the driver already supports. So if the eDMA driver already supports the software interface for "fsl,imx8qm-edma" and the IP block is compatible with this, we add this to the DT, so the we don't need any driver changes just to support a new SoC. But as you can never be sure if there are subtle differences in the IP block and/or SOC integration when adding the DT support, we also add a more specific compatible to the DT. If it turns out that there are software visible differences, we only need to adapt the driver to check for the more specific compatible to trigger the changed behavior, allowing to keep the DT stable. Regards, Lucas ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes 2019-03-27 9:33 ` Lucas Stach @ 2019-03-27 16:36 ` Daniel Baluta 0 siblings, 0 replies; 7+ messages in thread From: Daniel Baluta @ 2019-03-27 16:36 UTC (permalink / raw) To: Lucas Stach Cc: Aisheng Dong, mark.rutland, devicetree, Peng Fan, festevam, Anson Huang, Teo Hall, Daniel Baluta, s.hauer, linux-kernel, robh+dt, dl-linux-imx, kernel, shawnguo, S.j. Wang, linux-arm-kernel On Wed, Mar 27, 2019 at 11:33 AM Lucas Stach <l.stach@pengutronix.de> wrote: > > Hi Daniel, > > Am Mittwoch, den 27.03.2019, 10:51 +0200 schrieb Daniel Baluta: > [...] > > > > > or > > > "fsl,imx8qxp-edma", "fsl,imx8qm-edma"? > > > > One thing that it is not clear for me is why there are places > > where we use two compatible strings? > > > > I understand the situation where are two distinct drivers, but is there > > any other reason to add multiple compatible strings for a node in dts? > > We use 2 compatible string where there should not be any differences > between the IP blocks of this SoC and a version the driver already > supports. > > So if the eDMA driver already supports the software interface for > "fsl,imx8qm-edma" and the IP block is compatible with this, we add this > to the DT, so the we don't need any driver changes just to support a > new SoC. But as you can never be sure if there are subtle differences > in the IP block and/or SOC integration when adding the DT support, we > also add a more specific compatible to the DT. If it turns out that > there are software visible differences, we only need to adapt the > driver to check for the more specific compatible to trigger the changed > behavior, allowing to keep the DT stable. Excellent explanation Lucas! For the moment upstream eDMA driver doesn't have support for any i.MX8 so I think using "fsl,imx8qxp-edma" should be acceptable. Thanks, Daniel. ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2019-03-27 16:36 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2019-03-26 9:42 [PATCH 0/2] Add EDMA0/EDMA1 nodes Daniel Baluta 2019-03-26 9:43 ` [PATCH 1/2] bindings: fsl-edma: Document fsl,imx8qm-edma compatbile string Daniel Baluta 2019-03-26 9:43 ` [PATCH 2/2] arm64: dts: imx8qxp: Add EDMA0/EDMA1 nodes Daniel Baluta 2019-03-26 13:30 ` Aisheng Dong 2019-03-27 8:51 ` Daniel Baluta 2019-03-27 9:33 ` Lucas Stach 2019-03-27 16:36 ` Daniel Baluta
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