[GIT PULL] EDAC pile for 5.2

[GIT PULL] EDAC pile for 5.2

[Borislav Petkov]

Hi Linus,

here's the pile which accumulated this cycle in EDAC-land.

Please pull,
thx.

---
The following changes since commit 9e98c678c2d6ae3a17cb2de55d17f69dddaa231b:

  Linux 5.1-rc1 (2019-03-17 14:22:26 -0700)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git tags/edac_for_5.2

for you to fetch changes up to 8de9930a4618811edfaebc4981a9fafff2af9170:

  Revert "EDAC/amd64: Support more than two controllers for chip select handling" (2019-04-25 16:30:34 +0200)

----------------------------------------------------------------
* amd64_edac: Family 0x17, models 0x30-.. enablement (Yazen Ghannam)

* skx_*: Librarize it so that it can be shared between drivers (Qiuxu Zhuo)

* altera: Stratix10 improvements (Thor Thayer)

* The usual round of fixes, fixlets and cleanups

----------------------------------------------------------------
Borislav Petkov (1):
      Revert "EDAC/amd64: Support more than two controllers for chip select handling"

Qiuxu Zhuo (1):
      EDAC, skx, i10nm: Make skx_common.c a pure library

Thor Thayer (7):
      EDAC, altera: Fix S10 Double Bit Error Notification
      EDAC/altera: Do less intrusive error injection
      EDAC/altera: Initialize peripheral FIFOs in probe()
      EDAC/altera, firmware/intel: Add Stratix10 ECC DBE SMC call
      Documentation: dt: edac: Fix Stratix10 IRQ bindings
      Documentation: dt: edac: Add Stratix10 Peripheral bindings
      arm64: dts: stratix10: Use new Stratix10 EDAC bindings

Tony Luck (2):
      MAINTAINERS: Update entry for EDAC-SKYLAKE
      MAINTAINERS: Add entry for EDAC-I10NM

Yazen Ghannam (7):
      EDAC/amd64: Add Family 17h Model 30h PCI IDs
      EDAC/amd64: Use a macro for iterating over Unified Memory Controllers
      EDAC/amd64: Support more than two Unified Memory Controllers
      EDAC/amd64: Set maximum channel layer size depending on family
      EDAC/amd64: Recognize x16 symbol size
      EDAC/amd64: Support more than two controllers for chip select handling
      EDAC/amd64: Adjust printed chip select sizes when interleaved

 .../devicetree/bindings/edac/socfpga-eccmgr.txt    | 135 ++++++++++-
 MAINTAINERS                                        |   8 +-
 arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi  |  25 +-
 drivers/edac/altera_edac.c                         | 262 ++++++++++++---------
 drivers/edac/altera_edac.h                         |  69 +-----
 drivers/edac/amd64_edac.c                          | 135 ++++++++---
 drivers/edac/amd64_edac.h                          |  11 +-
 drivers/edac/i10nm_base.c                          |  52 +++-
 drivers/edac/skx_base.c                            |  50 +++-
 drivers/edac/skx_common.c                          |  57 +----
 drivers/edac/skx_common.h                          |   8 -
 include/linux/firmware/intel/stratix10-smc.h       |  19 ++
 12 files changed, 537 insertions(+), 294 deletions(-)

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Mary Higgins, Sri Rasiah, HRB 21284 (AG Nürnberg)

Re: [GIT PULL] EDAC pile for 5.2

[pr-tracker-bot]

The pull request you sent on Mon, 6 May 2019 10:37:32 +0200:

> git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp.git tags/edac_for_5.2

has been merged into torvalds/linux.git:
https://git.kernel.org/torvalds/c/275b103a26e218b3d739e5ab15be6b40303a1428

Thank you!

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