* [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add CPSW9G nodes
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
@ 2023-03-15 6:23 ` Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 2/4] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode Siddharth Vadapalli
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15 6:23 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
krzysztof.kozlowski+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
TI's J721E SoC has a 9 port Ethernet Switch instance with 8 external
ports and 1 host port, referred to as CPSW9G.
Add device-tree nodes for CPSW9G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 116 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
2 files changed, 117 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index c935622f0102..44f2833c5187 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -61,6 +61,13 @@ serdes_ln_ctrl: mux-controller@4080 {
<J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j721e-cpsw9g-phy-gmii-sel";
+ ti,qsgmii-main-ports = <2>, <2>;
+ reg = <0x4044 0x20>;
+ #phy-cells = <1>;
+ };
+
usb_serdes_mux: mux-controller@4000 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -404,6 +411,115 @@ cpts@310d0000 {
};
};
+ cpsw0: ethernet@c000000 {
+ compatible = "ti,j721e-cpswxg-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x0 0xc000000 0x0 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x0 0x0 0x0 0x0c000000 0x0 0x200000>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpsw0_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ status = "disabled";
+ };
+
+ cpsw0_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ status = "disabled";
+ };
+
+ cpsw0_port3: port@3 {
+ reg = <3>;
+ ti,mac-only;
+ label = "port3";
+ status = "disabled";
+ };
+
+ cpsw0_port4: port@4 {
+ reg = <4>;
+ ti,mac-only;
+ label = "port4";
+ status = "disabled";
+ };
+
+ cpsw0_port5: port@5 {
+ reg = <5>;
+ ti,mac-only;
+ label = "port5";
+ status = "disabled";
+ };
+
+ cpsw0_port6: port@6 {
+ reg = <6>;
+ ti,mac-only;
+ label = "port6";
+ status = "disabled";
+ };
+
+ cpsw0_port7: port@7 {
+ reg = <7>;
+ ti,mac-only;
+ label = "port7";
+ status = "disabled";
+ };
+
+ cpsw0_port8: port@8 {
+ reg = <8>;
+ ti,mac-only;
+ label = "port8";
+ status = "disabled";
+ };
+ };
+
+ cpsw9g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x0 0xf00 0x0 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 19 89>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x0 0x3d000 0x0 0x400>;
+ clocks = <&k3_clks 19 16>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_crypto: crypto@4e00000 {
compatible = "ti,j721e-sa2ul";
reg = <0x0 0x4e00000 0x0 0x1200>;
diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 6975cae644d9..ddbaa06e21bd 100644
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -135,6 +135,7 @@ cbass_main: bus@100000 {
<0x00 0x06000000 0x00 0x06000000 0x00 0x00400000>, /* USBSS0 */
<0x00 0x06400000 0x00 0x06400000 0x00 0x00400000>, /* USBSS1 */
<0x00 0x01000000 0x00 0x01000000 0x00 0x0af02400>, /* Most peripherals */
+ <0x00 0x0c000000 0x00 0x0c000000 0x00 0x0d000000>, /* CPSW9G */
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01800000>, /* PCIe Core*/
<0x00 0x0e000000 0x00 0x0e000000 0x00 0x01800000>, /* PCIe Core*/
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 2/4] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add CPSW9G nodes Siddharth Vadapalli
@ 2023-03-15 6:23 ` Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 3/4] arm64: dts: ti: j7200-main: Add CPSW5G nodes Siddharth Vadapalli
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15 6:23 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
krzysztof.kozlowski+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The J7 Quad Port Add-On Ethernet Card for J721E Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode.
Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.
Add aliases for CPSW9G ports to enable kernel to fetch MAC addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 3 +-
.../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 132 ++++++++++++++++++
2 files changed, 134 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 6acd12409d59..7ded6dacd3f2 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -31,8 +31,9 @@ dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
# Boards with J721e SoC
+k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
dtb-$(CONFIG_ARCH_K3) += k3-j721e-beagleboneai64.dtb
-dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
+dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb
# Boards with J721s2 SoC
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
new file mode 100644
index 000000000000..0acdb59d789b
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J721E board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/pinctrl/k3.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-cadence.h>
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+ ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
+ ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
+ };
+};
+
+&cpsw0 {
+ status = "okay";
+};
+
+&cpsw0_port1 {
+ status = "okay";
+ phy-handle = <&cpsw9g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+ status = "okay";
+ phy-handle = <&cpsw9g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+ status = "okay";
+ phy-handle = <&cpsw9g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+ status = "okay";
+ phy-handle = <&cpsw9g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw9g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw9g_phy0: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw9g_phy1: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw9g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw9g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "qsgmii-pwrdn-line";
+ };
+};
+
+&main_pmx0 {
+ mdio0_pins_default: mdio0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x1bc, PIN_OUTPUT, 0) /* (V24) MDIO0_MDC */
+ J721E_IOPAD(0x1b8, PIN_INPUT, 0) /* (V26) MDIO0_MDIO */
+ >;
+ };
+};
+
+&serdes_ln_ctrl {
+ idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_QSGMII_LANE2>,
+ <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
+ <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
+ <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
+ <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
+ <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
+};
+
+&serdes_wiz0 {
+ status = "okay";
+};
+
+&serdes0 {
+ status = "okay";
+
+ assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
+ assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ serdes0_qsgmii_link: phy@1 {
+ reg = <1>;
+ cdns,num-lanes = <1>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_QSGMII>;
+ resets = <&serdes_wiz0 2>;
+ };
+};
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 3/4] arm64: dts: ti: j7200-main: Add CPSW5G nodes
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 1/4] arm64: dts: ti: k3-j721e: Add CPSW9G nodes Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 2/4] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode Siddharth Vadapalli
@ 2023-03-15 6:23 ` Siddharth Vadapalli
2023-03-15 6:23 ` [PATCH v3 4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode Siddharth Vadapalli
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15 6:23 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
krzysztof.kozlowski+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
TI's J7200 SoC has a 5 port Ethernet Switch instance with 4 external
ports and 1 host port, referred to as CPSW5G.
Add device-tree nodes for CPSW5G and disable it by default. Device-tree
overlays will be used to enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 +++++++++++++++++++++++
1 file changed, 88 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index 138381f43ce4..abad0cb441ad 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -39,6 +39,13 @@ serdes_ln_ctrl: mux-controller@4080 {
<0x4088 0x3>, <0x408c 0x3>; /* SERDES0 lane2/3 select */
};
+ cpsw0_phy_gmii_sel: phy@4044 {
+ compatible = "ti,j7200-cpsw5g-phy-gmii-sel";
+ ti,qsgmii-main-ports = <1>;
+ reg = <0x4044 0x10>;
+ #phy-cells = <1>;
+ };
+
usb_serdes_mux: mux-controller@4000 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -304,6 +311,87 @@ cpts@310d0000 {
};
};
+ cpsw0: ethernet@c000000 {
+ compatible = "ti,j7200-cpswxg-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0xc000000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>;
+ clocks = <&k3_clks 19 33>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 19 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xca00>,
+ <&main_udmap 0xca01>,
+ <&main_udmap 0xca02>,
+ <&main_udmap 0xca03>,
+ <&main_udmap 0xca04>,
+ <&main_udmap 0xca05>,
+ <&main_udmap 0xca06>,
+ <&main_udmap 0xca07>,
+ <&main_udmap 0x4a00>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ cpsw0_port1: port@1 {
+ reg = <1>;
+ ti,mac-only;
+ label = "port1";
+ status = "disabled";
+ };
+
+ cpsw0_port2: port@2 {
+ reg = <2>;
+ ti,mac-only;
+ label = "port2";
+ status = "disabled";
+ };
+
+ cpsw0_port3: port@3 {
+ reg = <3>;
+ ti,mac-only;
+ label = "port3";
+ status = "disabled";
+ };
+
+ cpsw0_port4: port@4 {
+ reg = <4>;
+ ti,mac-only;
+ label = "port4";
+ status = "disabled";
+ };
+ };
+
+ cpsw5g_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio","ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 19 33>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ status = "disabled";
+ };
+
+ cpts@3d000 {
+ compatible = "ti,j721e-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 19 16>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_pmx0: pinctrl@11c000 {
compatible = "pinctrl-single";
/* Proxy 0 addressing */
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v3 4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
` (2 preceding siblings ...)
2023-03-15 6:23 ` [PATCH v3 3/4] arm64: dts: ti: j7200-main: Add CPSW5G nodes Siddharth Vadapalli
@ 2023-03-15 6:23 ` Siddharth Vadapalli
2023-03-15 14:48 ` [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Andrew Davis
2023-03-20 23:00 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Siddharth Vadapalli @ 2023-03-15 6:23 UTC (permalink / raw)
To: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski,
krzysztof.kozlowski+dt, afd
Cc: devicetree, linux-kernel, linux-arm-kernel, srk, s-vadapalli
The J7 Quad Port Add-On Ethernet Card for J7200 Common-Proc-Board supports
QSGMII mode. Use the overlay to configure CPSW5G ports in QSGMII mode.
Add support to reset the PHY from kernel by using gpio-hog and gpio-reset.
Add aliases for CPSW5G ports to enable kernel to fetch MAC addresses
directly from U-Boot.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
---
arch/arm64/boot/dts/ti/Makefile | 3 +-
.../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 100 ++++++++++++++++++
2 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index 7ded6dacd3f2..5312e4adc4e3 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -28,7 +28,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced-pg2.dtb
dtb-$(CONFIG_ARCH_K3) += k3-am654-base-board.dtb
# Boards with J7200 SoC
-dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
+k3-j7200-evm-dtbs := k3-j7200-common-proc-board.dtb k3-j7200-evm-quad-port-eth-exp.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j7200-evm.dtb
# Boards with J721e SoC
k3-j721e-evm-dtbs := k3-j721e-common-proc-board.dtb k3-j721e-evm-quad-port-eth-exp.dtbo
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
new file mode 100644
index 000000000000..78ba7bcedf3f
--- /dev/null
+++ b/arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
@@ -0,0 +1,100 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * DT Overlay for CPSW5G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with
+ * J7200 board.
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/pinctrl/k3.h>
+
+&{/} {
+ aliases {
+ ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@1";
+ ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@2";
+ ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@3";
+ ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@4";
+ };
+};
+
+&cpsw0 {
+ status = "okay";
+};
+
+&cpsw0_port1 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy0>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 1>;
+};
+
+&cpsw0_port2 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy1>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 2>;
+};
+
+&cpsw0_port3 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy2>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 3>;
+};
+
+&cpsw0_port4 {
+ status = "okay";
+ phy-handle = <&cpsw5g_phy3>;
+ phy-mode = "qsgmii";
+ mac-address = [00 00 00 00 00 00];
+ phys = <&cpsw0_phy_gmii_sel 4>;
+};
+
+&cpsw5g_mdio {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&mdio0_pins_default>;
+ reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>;
+ reset-post-delay-us = <120000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpsw5g_phy0: ethernet-phy@16 {
+ reg = <16>;
+ };
+ cpsw5g_phy1: ethernet-phy@17 {
+ reg = <17>;
+ };
+ cpsw5g_phy2: ethernet-phy@18 {
+ reg = <18>;
+ };
+ cpsw5g_phy3: ethernet-phy@19 {
+ reg = <19>;
+ };
+};
+
+&exp2 {
+ qsgmii-line-hog {
+ gpio-hog;
+ gpios = <16 GPIO_ACTIVE_HIGH>;
+ output-low;
+ line-name = "qsgmii-pwrdn-line";
+ };
+};
+
+&main_pmx0 {
+ mdio0_pins_default: mdio0-pins-default {
+ pinctrl-single,pins = <
+ J721E_IOPAD(0x00a8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */
+ J721E_IOPAD(0x00a4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */
+ >;
+ };
+};
--
2.25.1
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
` (3 preceding siblings ...)
2023-03-15 6:23 ` [PATCH v3 4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode Siddharth Vadapalli
@ 2023-03-15 14:48 ` Andrew Davis
2023-03-20 23:00 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Andrew Davis @ 2023-03-15 14:48 UTC (permalink / raw)
To: Siddharth Vadapalli, nm, vigneshr, kristo, robh+dt,
krzysztof.kozlowski, krzysztof.kozlowski+dt
Cc: devicetree, linux-kernel, linux-arm-kernel, srk
On 3/15/23 1:23 AM, Siddharth Vadapalli wrote:
> Hello,
>
> This series adds the device-tree nodes for the CPSW9G instance of CPSW
> Ethernet Switch on TI's J721E SoC and the CPSW5G instance of CPSW
> Ethernet Switch on TI's J7200 SoC. Additionally, overlays are also added
> to individually enable CPSW9G on J721E SoC and CPSW5G on J7200 SoC in
> QSGMII mode with the Add-On J7 QUAD Port Ethernet expansion QSGMII
> daughtercard.
>
> This series combines the v2 series for J721E CPSW9G at:
> https://lore.kernel.org/r/20230310103504.731845-1-s-vadapalli@ti.com/
> and the v1 series for J7200 CPSW5G at:
> https://lore.kernel.org/r/20230310101407.722334-1-s-vadapalli@ti.com/
>
> The suggestions for the v2 series for J721E are implemented for the J7200
> series as well in this patch series.
>
Looks much better, thanks for the changes,
Reviewed-by: Andrew Davis <afd@ti.com>
> ---
> Changes from v2 for J721E CPSW9G series:
> 1. Rename the overlay k3-j721e-quad-port-eth-exp.dtso as
> k3-j721e-evm-quad-port-eth-exp.dtso.
> 2. Update arch/arm64/boot/dts/ti/Makefile to build k3-j721e-evm.dtb as the
> result of applying k3-j721e-evm-quad-port-eth-exp.dtbo to
> k3-j721e-common-proc-board.dtb.
> 3. Use the newer "&{/} {" style instead of the "fragments" style in
> k3-j721e-evm-quad-port-eth-exp.dtso.
> 4. Move the "mdio0_pins_default" pinctrl from cpsw0 node into the
> "cpsw9g_mdio" node.
> 5. Disable individual "cpsw0_port" nodes in the main.dtsi file, enabling
> only the required nodes in the overlay.
> 6. Disable the "cpsw9g_mdio" node in the main.dtsi file.
>
> Changes from v1 for J721E CPSW9G series:
> 1. Rename node name "mdio_pins_default" to "mdio0-pins-default", since
> node names shouldn't contain underscores.
> 2. Change node label "mdio_pins_default" to "mdio0_pins_default".
>
> Changes from v1 for J7200 CPSW5G series:
> 1. Rename the overlay k3-j7200-quad-port-eth-exp.dtso as
> k3-j7200-evm-quad-port-eth-exp.dtso.
> 2. Update arch/arm64/boot/dts/ti/Makefile to build k3-j7200-evm.dtb as the
> result of applying k3-j7200-evm-quad-port-eth-exp.dtbo to
> k3-j7200-common-proc-board.dtb.
> 3. Use the newer "&{/} {" style instead of the "fragments" style in
> k3-j7200-evm-quad-port-eth-exp.dtso.
> 4. Move the "mdio0_pins_default" pinctrl from cpsw0 node into the
> "cpsw5g_mdio" node.
> 5. Disable individual "cpsw0_port" nodes in the main.dtsi file, enabling
> only the required nodes in the overlay.
> 6. Disable the "cpsw5g_mdio" node in the main.dtsi file.
>
> J721E CPSW9G v2 series:
> https://lore.kernel.org/r/20230310103504.731845-1-s-vadapalli@ti.com/
> J721E CPSW9G v1 series:
> https://lore.kernel.org/r/20230310092804.692303-1-s-vadapalli@ti.com/
> J7200 CPSW5G v1 series:
> https://lore.kernel.org/r/20230310101407.722334-1-s-vadapalli@ti.com/
>
> Siddharth Vadapalli (4):
> arm64: dts: ti: k3-j721e: Add CPSW9G nodes
> arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII
> mode
> arm64: dts: ti: j7200-main: Add CPSW5G nodes
> arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII
> mode
>
> arch/arm64/boot/dts/ti/Makefile | 6 +-
> .../ti/k3-j7200-evm-quad-port-eth-exp.dtso | 100 +++++++++++++
> arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 88 ++++++++++++
> .../ti/k3-j721e-evm-quad-port-eth-exp.dtso | 132 ++++++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 116 +++++++++++++++
> arch/arm64/boot/dts/ti/k3-j721e.dtsi | 1 +
> 6 files changed, 441 insertions(+), 2 deletions(-)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j7200-evm-quad-port-eth-exp.dtso
> create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-evm-quad-port-eth-exp.dtso
>
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G
2023-03-15 6:23 [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Siddharth Vadapalli
` (4 preceding siblings ...)
2023-03-15 14:48 ` [PATCH v3 0/4] Add DT support for J721E CPSW9G and J7200 CPSW5G Andrew Davis
@ 2023-03-20 23:00 ` Nishanth Menon
5 siblings, 0 replies; 7+ messages in thread
From: Nishanth Menon @ 2023-03-20 23:00 UTC (permalink / raw)
To: vigneshr, kristo, robh+dt, krzysztof.kozlowski,
krzysztof.kozlowski+dt, afd, Siddharth Vadapalli
Cc: Nishanth Menon, devicetree, linux-kernel, linux-arm-kernel, srk
Hi Siddharth Vadapalli,
On Wed, 15 Mar 2023 11:53:03 +0530, Siddharth Vadapalli wrote:
> This series adds the device-tree nodes for the CPSW9G instance of CPSW
> Ethernet Switch on TI's J721E SoC and the CPSW5G instance of CPSW
> Ethernet Switch on TI's J7200 SoC. Additionally, overlays are also added
> to individually enable CPSW9G on J721E SoC and CPSW5G on J7200 SoC in
> QSGMII mode with the Add-On J7 QUAD Port Ethernet expansion QSGMII
> daughtercard.
>
> [...]
I have applied the following to branch ti-k3-dts-next on [1].
Thank you!
[1/4] arm64: dts: ti: k3-j721e: Add CPSW9G nodes
commit: a2ff7f1108f6eeaa73a60378ed891b634a3bba61
[2/4] arm64: dts: ti: k3-j721e: Add overlay to enable CPSW9G ports in QSGMII mode
commit: 86e7de8bf908a03ac8fba4afeef25c54a1c2ef4a
[3/4] arm64: dts: ti: j7200-main: Add CPSW5G nodes
commit: d3bac98015da55866891054a2aeb42af7904fca8
[4/4] arm64: dts: ti: k3-j7200: Add overlay to enable CPSW5G ports in QSGMII mode
commit: 496cdc82e05f5683cdca5ab157938091e7744c95
All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent up the chain during
the next merge window (or sooner if it is a relevant bug fix), however if
problems are discovered then the patch may be dropped or reverted.
You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.
If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.
Please add any relevant lists and maintainers to the CCs when replying
to this mail.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 7+ messages in thread