* [PATCH] sparc: populate sysfs cache topology information on sun4v @ 2026-10-18 22:27 Jan Engelhardt 2026-10-19 0:16 ` Tony Rodriguez 2026-10-19 9:49 ` Stian Halseth 0 siblings, 2 replies; 6+ messages in thread From: Jan Engelhardt @ 2026-10-18 22:27 UTC (permalink / raw) To: davem; +Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz, Stian Halseth The SPARC port does not publish any cache topology information. The lscpu utility therefore falls back to assuming the published cache sizes are for unshared caches, and as a result, reports way more cache than there really is present in the system. On a T5240 machine: ``` $ lscpu Architecture: sparc64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Big Endian CPU(s): 128 On-line CPU(s) list: 0-127 Model name: UltraSparc T2 (Niagara2) Thread(s) per core: 4 Core(s) per socket: 16 Socket(s): 2 Flags: sun4v Caches (sum of all): L1d: 1 MiB (128 instances) L1i: 2 MiB (128 instances) L2: 512 MiB (128 instances) ``` This patch implements population of the sysfs cacheinfo structures for sun4v (systems with mdesc). The proper amount is now reflected in lscpu's output: ``` Caches (sum of all): L1d: 128 KiB (16 instances) L1i: 256 KiB (16 instances) L2: 8 MiB (2 instances) ``` Signed-off-by: Jan Engelhardt <jengelh@inai.de> --- arch/sparc/include/asm/cpudata_64.h | 8 +++- arch/sparc/kernel/mdesc.c | 61 +++++++++++++++++++++++++++++ 2 files changed, 68 insertions(+), 1 deletion(-) diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h index 056b3c0e7ef9..e28b841ffe23 100644 --- a/arch/sparc/include/asm/cpudata_64.h +++ b/arch/sparc/include/asm/cpudata_64.h @@ -18,13 +18,19 @@ typedef struct { unsigned int irq0_irqs; unsigned int __pad2; - /* Dcache line 2, rarely used */ + /* Dcache line 2+3, rarely used */ unsigned int dcache_size; unsigned int dcache_line_size; + unsigned int dcache_assoc; + unsigned int dcache_id; unsigned int icache_size; unsigned int icache_line_size; + unsigned int icache_assoc; + unsigned int icache_id; unsigned int ecache_size; unsigned int ecache_line_size; + unsigned int ecache_assoc; + unsigned int ecache_id; unsigned short sock_id; /* physical package */ unsigned short core_id; unsigned short max_cache_id; /* groupings of highest shared cache */ diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c index 23b51a32e96e..029d9d812074 100644 --- a/arch/sparc/kernel/mdesc.c +++ b/arch/sparc/kernel/mdesc.c @@ -818,6 +818,7 @@ static void fill_in_one_cache(cpuinfo_sparc *c, struct mdesc_handle *hp, u64 mp) const u64 *level = mdesc_get_property(hp, mp, "level", NULL); const u64 *size = mdesc_get_property(hp, mp, "size", NULL); const u64 *line_size = mdesc_get_property(hp, mp, "line-size", NULL); + const u64 *assoc = mdesc_get_property(hp, mp, "associativity", NULL); const char *type; int type_len; @@ -828,15 +829,21 @@ static void fill_in_one_cache(cpuinfo_sparc *c, struct mdesc_handle *hp, u64 mp) if (of_find_in_proplist(type, "instn", type_len)) { c->icache_size = *size; c->icache_line_size = *line_size; + c->icache_assoc = assoc ? *assoc : 0; + c->icache_id = mp; } else if (of_find_in_proplist(type, "data", type_len)) { c->dcache_size = *size; c->dcache_line_size = *line_size; + c->dcache_assoc = assoc ? *assoc : 0; + c->dcache_id = mp; } break; case 2: c->ecache_size = *size; c->ecache_line_size = *line_size; + c->ecache_assoc = assoc ? *assoc : 0; + c->ecache_id = mp; break; default: @@ -1251,6 +1258,60 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask) smp_fill_in_sib_core_maps(); } +int init_cache_level(unsigned int cpu) +{ + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); + i->num_levels = 2; + i->num_leaves = 3; + return 0; +} + +int populate_cache_leaves(unsigned int cpu) +{ + struct cacheinfo *leaf = get_cpu_cacheinfo(cpu)->info_list; + cpuinfo_sparc *cs = &cpu_data(cpu); + + leaf->id = cs->icache_id; + leaf->attributes = CACHE_ID; + leaf->level = 1; + leaf->type = CACHE_TYPE_INST; + leaf->coherency_line_size = cs->icache_line_size; + leaf->ways_of_associativity = cs->icache_assoc; + leaf->size = cs->icache_size; + leaf->priv = cs; + if (cs->icache_line_size > 0 && cs->icache_assoc > 0) + leaf->number_of_sets = cs->icache_size / cs->icache_line_size / + cs->icache_assoc; + ++leaf; + + leaf->id = cs->dcache_id; + leaf->attributes = CACHE_ID; + leaf->level = 1; + leaf->type = CACHE_TYPE_DATA; + leaf->coherency_line_size = cs->dcache_line_size; + leaf->ways_of_associativity = cs->dcache_assoc; + leaf->size = cs->dcache_size; + leaf->priv = cs; + if (cs->dcache_line_size > 0 && cs->dcache_assoc > 0) + leaf->number_of_sets = cs->dcache_size / cs->dcache_line_size / + cs->dcache_assoc; + ++leaf; + + leaf->id = cs->ecache_id; + leaf->attributes = CACHE_ID; + leaf->level = 2; + leaf->type = CACHE_TYPE_UNIFIED; + leaf->coherency_line_size = cs->ecache_line_size; + leaf->ways_of_associativity = cs->ecache_assoc; + leaf->size = cs->ecache_size; + leaf->priv = cs; + if (cs->ecache_line_size > 0 && cs->ecache_assoc > 0) + leaf->number_of_sets = cs->ecache_size / cs->ecache_line_size / + cs->ecache_assoc; + + return 0; +} + /* mdesc_open() - Grab a reference to mdesc_handle when /dev/mdesc is * opened. Hold this reference until /dev/mdesc is closed to ensure * mdesc data structure is not released underneath us. Store the -- 2.56.0 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sparc: populate sysfs cache topology information on sun4v 2026-10-18 22:27 [PATCH] sparc: populate sysfs cache topology information on sun4v Jan Engelhardt @ 2026-10-19 0:16 ` Tony Rodriguez 2026-10-19 0:37 ` Tony Rodriguez 2026-10-19 9:49 ` Stian Halseth 1 sibling, 1 reply; 6+ messages in thread From: Tony Rodriguez @ 2026-10-19 0:16 UTC (permalink / raw) To: Jan Engelhardt, davem Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz, Stian Halseth Hi Jan, On 10/18/26 3:27 PM, Jan Engelhardt wrote: > The SPARC port does not publish any cache topology information. The > lscpu utility therefore falls back to assuming the published cache > sizes are for unshared caches, and as a result, reports way more > cache than there really is present in the system. On a T5240 machine: > > ``` > $ lscpu > Architecture: sparc64 > CPU op-mode(s): 32-bit, 64-bit > Byte Order: Big Endian > CPU(s): 128 > On-line CPU(s) list: 0-127 > Model name: UltraSparc T2 (Niagara2) > Thread(s) per core: 4 > Core(s) per socket: 16 > Socket(s): 2 > Flags: sun4v > Caches (sum of all): > L1d: 1 MiB (128 instances) > L1i: 2 MiB (128 instances) > L2: 512 MiB (128 instances) > ``` > > This patch implements population of the sysfs cacheinfo structures > for sun4v (systems with mdesc). The proper amount is now reflected in > lscpu's output: > > ``` > Caches (sum of all): > L1d: 128 KiB (16 instances) > L1i: 256 KiB (16 instances) > L2: 8 MiB (2 instances) > ``` > > Signed-off-by: Jan Engelhardt <jengelh@inai.de> > --- > arch/sparc/include/asm/cpudata_64.h | 8 +++- > arch/sparc/kernel/mdesc.c | 61 +++++++++++++++++++++++++++++ > 2 files changed, 68 insertions(+), 1 deletion(-) > > diff --git a/arch/sparc/include/asm/cpudata_64.h b/arch/sparc/include/asm/cpudata_64.h > index 056b3c0e7ef9..e28b841ffe23 100644 > --- a/arch/sparc/include/asm/cpudata_64.h > +++ b/arch/sparc/include/asm/cpudata_64.h > @@ -18,13 +18,19 @@ typedef struct { > unsigned int irq0_irqs; > unsigned int __pad2; > > - /* Dcache line 2, rarely used */ > + /* Dcache line 2+3, rarely used */ > unsigned int dcache_size; > unsigned int dcache_line_size; > + unsigned int dcache_assoc; > + unsigned int dcache_id; > unsigned int icache_size; > unsigned int icache_line_size; > + unsigned int icache_assoc; > + unsigned int icache_id; > unsigned int ecache_size; > unsigned int ecache_line_size; > + unsigned int ecache_assoc; > + unsigned int ecache_id; > unsigned short sock_id; /* physical package */ > unsigned short core_id; > unsigned short max_cache_id; /* groupings of highest shared cache */ > diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c > index 23b51a32e96e..029d9d812074 100644 > --- a/arch/sparc/kernel/mdesc.c > +++ b/arch/sparc/kernel/mdesc.c > @@ -818,6 +818,7 @@ static void fill_in_one_cache(cpuinfo_sparc *c, struct mdesc_handle *hp, u64 mp) > const u64 *level = mdesc_get_property(hp, mp, "level", NULL); > const u64 *size = mdesc_get_property(hp, mp, "size", NULL); > const u64 *line_size = mdesc_get_property(hp, mp, "line-size", NULL); > + const u64 *assoc = mdesc_get_property(hp, mp, "associativity", NULL); > const char *type; > int type_len; > > @@ -828,15 +829,21 @@ static void fill_in_one_cache(cpuinfo_sparc *c, struct mdesc_handle *hp, u64 mp) > if (of_find_in_proplist(type, "instn", type_len)) { > c->icache_size = *size; > c->icache_line_size = *line_size; > + c->icache_assoc = assoc ? *assoc : 0; > + c->icache_id = mp; > } else if (of_find_in_proplist(type, "data", type_len)) { > c->dcache_size = *size; > c->dcache_line_size = *line_size; > + c->dcache_assoc = assoc ? *assoc : 0; > + c->dcache_id = mp; > } > break; > > case 2: > c->ecache_size = *size; > c->ecache_line_size = *line_size; > + c->ecache_assoc = assoc ? *assoc : 0; > + c->ecache_id = mp; > break; > > default: > @@ -1251,6 +1258,60 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask) > smp_fill_in_sib_core_maps(); > } > > +int init_cache_level(unsigned int cpu) > +{ > + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); > + i->num_levels = 2; > + i->num_leaves = 3; > + return 0; > +} > + > +int populate_cache_leaves(unsigned int cpu) > +{ > + struct cacheinfo *leaf = get_cpu_cacheinfo(cpu)->info_list; > + cpuinfo_sparc *cs = &cpu_data(cpu); > + > + leaf->id = cs->icache_id; > + leaf->attributes = CACHE_ID; > + leaf->level = 1; > + leaf->type = CACHE_TYPE_INST; > + leaf->coherency_line_size = cs->icache_line_size; > + leaf->ways_of_associativity = cs->icache_assoc; > + leaf->size = cs->icache_size; > + leaf->priv = cs; > + if (cs->icache_line_size > 0 && cs->icache_assoc > 0) > + leaf->number_of_sets = cs->icache_size / cs->icache_line_size / > + cs->icache_assoc; > + ++leaf; > + > + leaf->id = cs->dcache_id; > + leaf->attributes = CACHE_ID; > + leaf->level = 1; > + leaf->type = CACHE_TYPE_DATA; > + leaf->coherency_line_size = cs->dcache_line_size; > + leaf->ways_of_associativity = cs->dcache_assoc; > + leaf->size = cs->dcache_size; > + leaf->priv = cs; > + if (cs->dcache_line_size > 0 && cs->dcache_assoc > 0) > + leaf->number_of_sets = cs->dcache_size / cs->dcache_line_size / > + cs->dcache_assoc; > + ++leaf; > + > + leaf->id = cs->ecache_id; > + leaf->attributes = CACHE_ID; > + leaf->level = 2; > + leaf->type = CACHE_TYPE_UNIFIED; > + leaf->coherency_line_size = cs->ecache_line_size; > + leaf->ways_of_associativity = cs->ecache_assoc; > + leaf->size = cs->ecache_size; > + leaf->priv = cs; > + if (cs->ecache_line_size > 0 && cs->ecache_assoc > 0) > + leaf->number_of_sets = cs->ecache_size / cs->ecache_line_size / > + cs->ecache_assoc; > + > + return 0; > +} > + > /* mdesc_open() - Grab a reference to mdesc_handle when /dev/mdesc is > * opened. Hold this reference until /dev/mdesc is closed to ensure > * mdesc data structure is not released underneath us. Store the Thanks for working on this — publishing proper SPARC cache topology is long overdue, and reading associativity from MDESC plus carrying cache IDs through cpuinfo_sparc is a sensible direction. *Full disclosure: I ran this patch through "DeepSeek AI" out of curiosity to sanity-check it and I am interested in learning more. Deep Seek AI flagged a few issues that seem worth mentioning: You may want to double check the "Deep Seek AI" review of this patch. Main blockers 1) leaf->attributes = CACHE_ID is invalid. attributes is a bitmask of CACHE_WRITE_BACK / CACHE_WRITE_THROUGH / etc.; CACHE_ID isn’t a valid attribute. It should be 0 or real attribute bits from MDESC. 2) Shared-cache reporting is not actually wired up, so T2-class machines still show the wrong cache sizes. The patch sets leaf->id = mp and leaf->priv = cs, but never fills leaf->shared_cpu_map, and the generic detect_cache_attributes() -> cache_shared_cpu_map_setup() path doesn’t appear to be invoked on SPARC. As a result, the generic cacheinfo code still treats every leaf as private to one CPU, and lscpu still multiplies shared cache size by the number of threads — the exact bug being reported. Concretely: with this patch applied, a T5240 would still report L2: 512 MiB (128 instances) rather than the correct L2: 8 MiB (2 instances) (4 MB per socket, shared across 64 threads, 2 sockets). A T5120 would still report the 4 MB shared L2 as 4 MB × 64 threads = 256 MiB in 64 instances , instead of 4 MiB (1 instance). The patch does not change the outcome on T2-class hardware because the leaves are still treated as private to each CPU. 3) MDESC level handling is incomplete and mislabels caches on S7/T7. fill_in_one_cache() only handles case 1: (L1I/L1D) and case 2: (ecache); everything else falls through to default:. On T2/T5240 that happens to work because the shared 4 MB is reported at level 2. But on S7-2/T7-1, MDESC reports L2 at level 2 and the shared L3 at level 3 — so the L2 gets stored as ecache_*, and the real L3 is silently ignored. cpuinfo_sparc also has no separate l2_* fields, so the data model can’t hold both levels. 4) Hardcoded num_levels = 2 / num_leaves = 3 and ecache labeled level 2 are wrong across the family. T2/T5240: L1I + L1D + shared L2 (no L3). S7-2: L1 + shared L2 + shared L3. T7-1: L1 + private L2 + shared L3. The leaf count, levels, and types need to be derived from MDESC, not hardcoded. 5) The new init_cache_level() / populate_cache_leaves() don’t appear to be wired into the generic cacheinfo path , so they may never actually be called. Additional issues 6) leaf->id is int, but the patch stores a truncated u64 MDESC handle. ecache_id/ icache_id/ dcache_id are unsigned int, assigned from u64 mp. Beyond truncation, assigning u32 → int id can produce negative IDs. An index-based or hashed ID would be cleaner. 7) Growing cpuinfo_sparc needs an asm-offset audit. The struct has a “must be 1st” field and SPARC asm accesses cpu_data at fixed offsets in places like rtrap_64.S. The patch adds fields after that, so offset 0 is preserved, but it should be confirmed that no asm hardcodes offsets into the fields that now shift ( sock_id, core_id, max_cache_id, cache fields). It also grows the per-CPU area past the “Dcache line 2” region. 8) The data model has no separate L2 storage for S7/T7. cpuinfo_sparc only has ecache_* for the shared cache. To model S7 (shared L2 per cluster + shared L3 per socket) and T7 (private L2 per core + shared L3), you need distinct l2_* and l3/ ecache_* fields. 9) The new *_id scheme duplicates existing infrastructure. cpuinfo_sparc already has max_cache_id (“groupings of highest shared cache”) and smp_fill_in_sib_core_maps(). It’s worth checking whether that mechanism should be extended rather than adding six new fields. 10) num_leaves may not exist in the target kernel. struct cpu_cacheinfo gained num_leaves relatively late (~4.16). If the tree is older, init_cache_level() won’t compile or won’t allocate the right number of leaves. 11) Missing validation / NULL checks. fill_in_one_cache() dereferences *size and *line_size without NULL checks (pre-existing, but adjacent to the new code). assoc is checked, which is good, but there’s no power-of-two validation, and when assoc == 0 the leaf still publishes a size with number_of_sets = 0, which lscpu may render oddly. 12) “ecache” naming is platform-dependent. Historically “ecache” meant L2 on older SPARC; on S7/T7 the external/shared cache is L3. Using ecache_* for both with a hardcoded level 2 is semantically confusing; the level should come from MDESC. 13) Style / linkage. The new functions should probably be static; there’s mixed indentation versus the file’s tabs; and a checkpatch.pl --strict run would be worthwhile. 14) Error paths always return 0. init_cache_level() and populate_cache_leaves() publish leaves even if all MDESC cache data is zero/absent, yielding zero-size cache leaves rather than “unknown.” 15) leaf->priv = cs is probably harmless, but worth confirming nothing in the generic path or arch code expects a particular priv type. A topology-driven fix — dynamic leaves from MDESC, correct levels, separate L2/L3 storage, and a shared_cpu_map keyed on sock_id/cluster — would make T2/T5240 report 8 MiB L2 in 2 instances and S7-2/T7-1 report their shared L3 correctly instead of 64× inflated. One clarification on the T5240 lscpu output, since it can look partly correct: the L1d: 1 MiB (128 instances) and L1i: 2 MiB (128 instances) lines are actually right — L1 really is private per core on T2, so 128 instances is correct. The L2 line is the giveaway: it reports 512 MiB (128 instances), i.e. 128 × 4 MB, when a dual-socket T5240 has only 2 shared 4 MB L2 caches (one per socket), for 8 MiB total in 2 instances . The default “every leaf is private” assumption happens to be true for L1 and false for L2, which is why only the L2 line is inflated. This patch, as written, would leave that L2 line unchanged. In short: on T2-class hardware (T5120/T5240) this patch produces the same incorrect lscpu output as unpatched mainline — it does not resolve the reported over-reporting there either. Regards, Tony ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sparc: populate sysfs cache topology information on sun4v 2026-10-19 0:16 ` Tony Rodriguez @ 2026-10-19 0:37 ` Tony Rodriguez 2026-10-19 2:32 ` Tony Rodriguez [not found] ` <c7d7a96c-feb9-4676-8cc2-73529e8324ef@gmail.com> 0 siblings, 2 replies; 6+ messages in thread From: Tony Rodriguez @ 2026-10-19 0:37 UTC (permalink / raw) To: Jan Engelhardt, davem Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz, Stian Halseth Hi Jan, On 10/18/26 5:16 PM, Tony Rodriguez wrote: > Hi Jan, > > On 10/18/26 3:27 PM, Jan Engelhardt wrote: >> The SPARC port does not publish any cache topology information. The >> lscpu utility therefore falls back to assuming the published cache >> sizes are for unshared caches, and as a result, reports way more >> cache than there really is present in the system. On a T5240 machine: >> >> ``` >> $ lscpu >> Architecture: sparc64 >> CPU op-mode(s): 32-bit, 64-bit >> Byte Order: Big Endian >> CPU(s): 128 >> On-line CPU(s) list: 0-127 >> Model name: UltraSparc T2 (Niagara2) >> Thread(s) per core: 4 >> Core(s) per socket: 16 >> Socket(s): 2 >> Flags: sun4v >> Caches (sum of all): >> L1d: 1 MiB (128 instances) >> L1i: 2 MiB (128 instances) >> L2: 512 MiB (128 instances) >> ``` >> >> This patch implements population of the sysfs cacheinfo structures >> for sun4v (systems with mdesc). The proper amount is now reflected in >> lscpu's output: >> >> ``` >> Caches (sum of all): >> L1d: 128 KiB (16 instances) >> L1i: 256 KiB (16 instances) >> L2: 8 MiB (2 instances) >> ``` >> >> Signed-off-by: Jan Engelhardt <jengelh@inai.de> >> --- >> arch/sparc/include/asm/cpudata_64.h | 8 +++- >> arch/sparc/kernel/mdesc.c | 61 +++++++++++++++++++++++++++++ >> 2 files changed, 68 insertions(+), 1 deletion(-) >> >> diff --git a/arch/sparc/include/asm/cpudata_64.h >> b/arch/sparc/include/asm/cpudata_64.h >> index 056b3c0e7ef9..e28b841ffe23 100644 >> --- a/arch/sparc/include/asm/cpudata_64.h >> +++ b/arch/sparc/include/asm/cpudata_64.h >> @@ -18,13 +18,19 @@ typedef struct { >> unsigned int irq0_irqs; >> unsigned int __pad2; >> - /* Dcache line 2, rarely used */ >> + /* Dcache line 2+3, rarely used */ >> unsigned int dcache_size; >> unsigned int dcache_line_size; >> + unsigned int dcache_assoc; >> + unsigned int dcache_id; >> unsigned int icache_size; >> unsigned int icache_line_size; >> + unsigned int icache_assoc; >> + unsigned int icache_id; >> unsigned int ecache_size; >> unsigned int ecache_line_size; >> + unsigned int ecache_assoc; >> + unsigned int ecache_id; >> unsigned short sock_id; /* physical package */ >> unsigned short core_id; >> unsigned short max_cache_id; /* groupings of highest shared >> cache */ >> diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c >> index 23b51a32e96e..029d9d812074 100644 >> --- a/arch/sparc/kernel/mdesc.c >> +++ b/arch/sparc/kernel/mdesc.c >> @@ -818,6 +818,7 @@ static void fill_in_one_cache(cpuinfo_sparc *c, >> struct mdesc_handle *hp, u64 mp) >> const u64 *level = mdesc_get_property(hp, mp, "level", NULL); >> const u64 *size = mdesc_get_property(hp, mp, "size", NULL); >> const u64 *line_size = mdesc_get_property(hp, mp, "line-size", >> NULL); >> + const u64 *assoc = mdesc_get_property(hp, mp, "associativity", >> NULL); >> const char *type; >> int type_len; >> @@ -828,15 +829,21 @@ static void fill_in_one_cache(cpuinfo_sparc >> *c, struct mdesc_handle *hp, u64 mp) >> if (of_find_in_proplist(type, "instn", type_len)) { >> c->icache_size = *size; >> c->icache_line_size = *line_size; >> + c->icache_assoc = assoc ? *assoc : 0; >> + c->icache_id = mp; >> } else if (of_find_in_proplist(type, "data", type_len)) { >> c->dcache_size = *size; >> c->dcache_line_size = *line_size; >> + c->dcache_assoc = assoc ? *assoc : 0; >> + c->dcache_id = mp; >> } >> break; >> case 2: >> c->ecache_size = *size; >> c->ecache_line_size = *line_size; >> + c->ecache_assoc = assoc ? *assoc : 0; >> + c->ecache_id = mp; >> break; >> default: >> @@ -1251,6 +1258,60 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask) >> smp_fill_in_sib_core_maps(); >> } >> +int init_cache_level(unsigned int cpu) >> +{ >> + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); >> + i->num_levels = 2; >> + i->num_leaves = 3; >> + return 0; >> +} >> + >> +int populate_cache_leaves(unsigned int cpu) >> +{ >> + struct cacheinfo *leaf = get_cpu_cacheinfo(cpu)->info_list; >> + cpuinfo_sparc *cs = &cpu_data(cpu); >> + >> + leaf->id = cs->icache_id; >> + leaf->attributes = CACHE_ID; >> + leaf->level = 1; >> + leaf->type = CACHE_TYPE_INST; >> + leaf->coherency_line_size = cs->icache_line_size; >> + leaf->ways_of_associativity = cs->icache_assoc; >> + leaf->size = cs->icache_size; >> + leaf->priv = cs; >> + if (cs->icache_line_size > 0 && cs->icache_assoc > 0) >> + leaf->number_of_sets = cs->icache_size / cs->icache_line_size / >> + cs->icache_assoc; >> + ++leaf; >> + >> + leaf->id = cs->dcache_id; >> + leaf->attributes = CACHE_ID; >> + leaf->level = 1; >> + leaf->type = CACHE_TYPE_DATA; >> + leaf->coherency_line_size = cs->dcache_line_size; >> + leaf->ways_of_associativity = cs->dcache_assoc; >> + leaf->size = cs->dcache_size; >> + leaf->priv = cs; >> + if (cs->dcache_line_size > 0 && cs->dcache_assoc > 0) >> + leaf->number_of_sets = cs->dcache_size / cs->dcache_line_size / >> + cs->dcache_assoc; >> + ++leaf; >> + >> + leaf->id = cs->ecache_id; >> + leaf->attributes = CACHE_ID; >> + leaf->level = 2; >> + leaf->type = CACHE_TYPE_UNIFIED; >> + leaf->coherency_line_size = cs->ecache_line_size; >> + leaf->ways_of_associativity = cs->ecache_assoc; >> + leaf->size = cs->ecache_size; >> + leaf->priv = cs; >> + if (cs->ecache_line_size > 0 && cs->ecache_assoc > 0) >> + leaf->number_of_sets = cs->ecache_size / cs->ecache_line_size / >> + cs->ecache_assoc; >> + >> + return 0; >> +} >> + >> /* mdesc_open() - Grab a reference to mdesc_handle when /dev/mdesc is >> * opened. Hold this reference until /dev/mdesc is closed to ensure >> * mdesc data structure is not released underneath us. Store the I need to correct my previous reply — parts of it were wrong, and I'd rather retract them clearly than leave them in the thread. The claim that the patch doesn't fix the L2 over-reporting was incorrect. I misread the "before" lscpu output in the message. L1d: 128 KiB (16 instances) L1i: 256 KiB (16 instances) L2: 8 MiB (2 instances) What may still be worth a look: These are the points from my earlier list that don't depend on the behavior claims I got wrong — but please treat them as questions and not assertions. leaf->id is int while the MDESC handle is u64; the *_id fields are unsigned int, so there's truncation (harmless if only equality matters, but worth a cast or a comment). Growing cpuinfo_sparc shifts sock_id / core_id / max_cache_id — worth confirming no SPARC asm hardcodes offsets into those. fill_in_one_cache() handles case 1: and case 2: only; if S7/T7 report L2 and L3 at different MDESC levels, it'd be worth confirming both are captured (the "after" output only covers T2, so this is untested territory rather than a known bug). num_leaves in struct cpu_cacheinfo is version-dependent; worth confirming the target tree has it. Apologies for the noise — I should have read the "before/after" pair more carefully before replying. The patch does what it says for T2, and my earlier message should be disregarded where it says otherwise. Regards, Tony ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sparc: populate sysfs cache topology information on sun4v 2026-10-19 0:37 ` Tony Rodriguez @ 2026-10-19 2:32 ` Tony Rodriguez [not found] ` <c7d7a96c-feb9-4676-8cc2-73529e8324ef@gmail.com> 1 sibling, 0 replies; 6+ messages in thread From: Tony Rodriguez @ 2026-10-19 2:32 UTC (permalink / raw) To: Jan Engelhardt, davem Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz, Stian Halseth Hi Jan, >> >> On 10/18/26 3:27 PM, Jan Engelhardt wrote: >>> The SPARC port does not publish any cache topology information. The >>> lscpu utility therefore falls back to assuming the published cache >>> sizes are for unshared caches, and as a result, reports way more >>> cache than there really is present in the system. On a T5240 machine: >>> >>> ``` >>> $ lscpu >>> Architecture: sparc64 >>> CPU op-mode(s): 32-bit, 64-bit >>> Byte Order: Big Endian >>> CPU(s): 128 >>> On-line CPU(s) list: 0-127 >>> Model name: UltraSparc T2 (Niagara2) >>> Thread(s) per core: 4 >>> Core(s) per socket: 16 >>> Socket(s): 2 >>> Flags: sun4v >>> Caches (sum of all): >>> L1d: 1 MiB (128 instances) >>> L1i: 2 MiB (128 instances) >>> L2: 512 MiB (128 instances) >>> ``` >>> >>> This patch implements population of the sysfs cacheinfo structures >>> for sun4v (systems with mdesc). The proper amount is now reflected in >>> lscpu's output: >>> >>> ``` >>> Caches (sum of all): >>> L1d: 128 KiB (16 instances) >>> L1i: 256 KiB (16 instances) >>> L2: 8 MiB (2 instances) >>> ``` >>> >>> Signed-off-by: Jan Engelhardt <jengelh@inai.de> >>> --- >>> arch/sparc/include/asm/cpudata_64.h | 8 +++- >>> arch/sparc/kernel/mdesc.c | 61 >>> +++++++++++++++++++++++++++++ >>> 2 files changed, 68 insertions(+), 1 deletion(-) >>> >>> diff --git a/arch/sparc/include/asm/cpudata_64.h >>> b/arch/sparc/include/asm/cpudata_64.h >>> index 056b3c0e7ef9..e28b841ffe23 100644 >>> --- a/arch/sparc/include/asm/cpudata_64.h >>> +++ b/arch/sparc/include/asm/cpudata_64.h >>> @@ -18,13 +18,19 @@ typedef struct { >>> unsigned int irq0_irqs; >>> unsigned int __pad2; >>> - /* Dcache line 2, rarely used */ >>> + /* Dcache line 2+3, rarely used */ >>> unsigned int dcache_size; >>> unsigned int dcache_line_size; >>> + unsigned int dcache_assoc; >>> + unsigned int dcache_id; >>> unsigned int icache_size; >>> unsigned int icache_line_size; >>> + unsigned int icache_assoc; >>> + unsigned int icache_id; >>> unsigned int ecache_size; >>> unsigned int ecache_line_size; >>> + unsigned int ecache_assoc; >>> + unsigned int ecache_id; >>> unsigned short sock_id; /* physical package */ >>> unsigned short core_id; >>> unsigned short max_cache_id; /* groupings of highest >>> shared cache */ >>> diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c >>> index 23b51a32e96e..029d9d812074 100644 >>> --- a/arch/sparc/kernel/mdesc.c >>> +++ b/arch/sparc/kernel/mdesc.c >>> @@ -818,6 +818,7 @@ static void fill_in_one_cache(cpuinfo_sparc *c, >>> struct mdesc_handle *hp, u64 mp) >>> const u64 *level = mdesc_get_property(hp, mp, "level", NULL); >>> const u64 *size = mdesc_get_property(hp, mp, "size", NULL); >>> const u64 *line_size = mdesc_get_property(hp, mp, "line-size", >>> NULL); >>> + const u64 *assoc = mdesc_get_property(hp, mp, "associativity", >>> NULL); >>> const char *type; >>> int type_len; >>> @@ -828,15 +829,21 @@ static void fill_in_one_cache(cpuinfo_sparc >>> *c, struct mdesc_handle *hp, u64 mp) >>> if (of_find_in_proplist(type, "instn", type_len)) { >>> c->icache_size = *size; >>> c->icache_line_size = *line_size; >>> + c->icache_assoc = assoc ? *assoc : 0; >>> + c->icache_id = mp; >>> } else if (of_find_in_proplist(type, "data", type_len)) { >>> c->dcache_size = *size; >>> c->dcache_line_size = *line_size; >>> + c->dcache_assoc = assoc ? *assoc : 0; >>> + c->dcache_id = mp; >>> } >>> break; >>> case 2: >>> c->ecache_size = *size; >>> c->ecache_line_size = *line_size; >>> + c->ecache_assoc = assoc ? *assoc : 0; >>> + c->ecache_id = mp; >>> break; >>> default: >>> @@ -1251,6 +1258,60 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask) >>> smp_fill_in_sib_core_maps(); >>> } >>> +int init_cache_level(unsigned int cpu) >>> +{ >>> + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); >>> + i->num_levels = 2; >>> + i->num_leaves = 3; >>> + return 0; >>> +} >>> + >>> +int populate_cache_leaves(unsigned int cpu) >>> +{ >>> + struct cacheinfo *leaf = get_cpu_cacheinfo(cpu)->info_list; >>> + cpuinfo_sparc *cs = &cpu_data(cpu); >>> + >>> + leaf->id = cs->icache_id; >>> + leaf->attributes = CACHE_ID; >>> + leaf->level = 1; >>> + leaf->type = CACHE_TYPE_INST; >>> + leaf->coherency_line_size = cs->icache_line_size; >>> + leaf->ways_of_associativity = cs->icache_assoc; >>> + leaf->size = cs->icache_size; >>> + leaf->priv = cs; >>> + if (cs->icache_line_size > 0 && cs->icache_assoc > 0) >>> + leaf->number_of_sets = cs->icache_size / >>> cs->icache_line_size / >>> + cs->icache_assoc; >>> + ++leaf; >>> + >>> + leaf->id = cs->dcache_id; >>> + leaf->attributes = CACHE_ID; >>> + leaf->level = 1; >>> + leaf->type = CACHE_TYPE_DATA; >>> + leaf->coherency_line_size = cs->dcache_line_size; >>> + leaf->ways_of_associativity = cs->dcache_assoc; >>> + leaf->size = cs->dcache_size; >>> + leaf->priv = cs; >>> + if (cs->dcache_line_size > 0 && cs->dcache_assoc > 0) >>> + leaf->number_of_sets = cs->dcache_size / >>> cs->dcache_line_size / >>> + cs->dcache_assoc; >>> + ++leaf; >>> + >>> + leaf->id = cs->ecache_id; >>> + leaf->attributes = CACHE_ID; >>> + leaf->level = 2; >>> + leaf->type = CACHE_TYPE_UNIFIED; >>> + leaf->coherency_line_size = cs->ecache_line_size; >>> + leaf->ways_of_associativity = cs->ecache_assoc; >>> + leaf->size = cs->ecache_size; >>> + leaf->priv = cs; >>> + if (cs->ecache_line_size > 0 && cs->ecache_assoc > 0) >>> + leaf->number_of_sets = cs->ecache_size / >>> cs->ecache_line_size / >>> + cs->ecache_assoc; >>> + >>> + return 0; >>> +} >>> + >>> /* mdesc_open() - Grab a reference to mdesc_handle when /dev/mdesc is >>> * opened. Hold this reference until /dev/mdesc is closed to ensure >>> * mdesc data structure is not released underneath us. Store the > I’ve applied the patch to a dual‑socket SPARC S7‑2 (16 cores total, 128 threads) and wanted to share the resulting lscpu output, since it clarifies what the patch fixes and what still needs work for 3‑level parts. Before the patch: L1d: 2 MiB (128 instances) L1i: 2 MiB (128 instances) L2: 32 MiB (128 instances) After the patch: L1d: 256 KiB (16 instances) L1i: 256 KiB (16 instances) L2: 2 MiB (8 instances) A) The L1 reporting is now correct. Each of the 16 cores has a private 16 KB L1I and 16 KB L1D, so 256 KiB in 16 instances is exactly right. The per‑thread inflation is gone for L1, and the sharing/instance counts are sensible. The generic leaf->id grouping is clearly doing its job. * B) L2 is only half‑reported on S7: This may be true for S7, T7, and T8 CPUs. For the L2 split (On S7): L2D: 256 KB shared by every 2 cores -> 8 instances × 256 KB = 2 MiB (matches the output) L2I: 256 KB shared by every 4 cores ->4 instances × 256 KB = 1 MiB (missing) So the total L2 on this box should be 3 MiB across 12 instances , or shown as separate L2D/L2I lines. It looks like MDESC reports the L2I and L2D nodes separately, and the current case 2: overwrites one with the other in ecache_*. Supporting S7 properly would need either separate storage for L2I/L2D or a way to handle multiple level‑2 nodes. * C) Need "level 3" cache details for (useful for T4, T5, S7, T7, T8). As expected, the S7’s 16 MB per‑socket L3 (32 MiB total, 2 instances on this box) does not appear at all. init_cache_level() hardcodes num_levels = 2 / num_leaves = 3, and fill_in_one_cache() has no case 3:, so the MDESC level‑3 node is dropped in default. Adding an L3 leaf may need? l3_* fields in cpuinfo_sparc, a case 3: in fill_in_one_cache(), num_levels = 3 / num_leaves = 4 in init_cache_level(), a 4th leaf in populate_cache_leaves(). For T7‑1/T8‑1 this would surface their 64 MiB per‑socket L3; for S7‑2 it would show 32 MiB in 2 instances (16 MiB per cpu). The T5240 result looks correct because that machine is 2‑level only, so the missing case 3: doesn’t show up there. Summary: The patch is an improvement but needs more work. It fixes the L1 (and L2D) inflation on S7‑2. To make it complete for the 3‑level SPARC parts, it needs improved L2I/L2D handling and an L3 leaf. It would be great to have L3 cache details shown via lscpu as well. Tested-By: Tony Rodriguez <unixpro1970@gmail.com> Regards, Tony ^ permalink raw reply [flat|nested] 6+ messages in thread
[parent not found: <c7d7a96c-feb9-4676-8cc2-73529e8324ef@gmail.com>]
* Re: [PATCH] sparc: populate sysfs cache topology information on sun4v [not found] ` <c7d7a96c-feb9-4676-8cc2-73529e8324ef@gmail.com> @ 2026-10-19 2:42 ` Tony Rodriguez 0 siblings, 0 replies; 6+ messages in thread From: Tony Rodriguez @ 2026-10-19 2:42 UTC (permalink / raw) To: Jan Engelhardt, davem Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz, Stian Halseth Hi Jan, On 10/18/26 7:29 PM, Tony Rodriguez wrote: > > Hi Jan, > >>> >>> On 10/18/26 3:27 PM, Jan Engelhardt wrote: >>>> The SPARC port does not publish any cache topology information. The >>>> lscpu utility therefore falls back to assuming the published cache >>>> sizes are for unshared caches, and as a result, reports way more >>>> cache than there really is present in the system. On a T5240 machine: >>>> >>>> ``` >>>> $ lscpu >>>> Architecture: sparc64 >>>> CPU op-mode(s): 32-bit, 64-bit >>>> Byte Order: Big Endian >>>> CPU(s): 128 >>>> On-line CPU(s) list: 0-127 >>>> Model name: UltraSparc T2 (Niagara2) >>>> Thread(s) per core: 4 >>>> Core(s) per socket: 16 >>>> Socket(s): 2 >>>> Flags: sun4v >>>> Caches (sum of all): >>>> L1d: 1 MiB (128 instances) >>>> L1i: 2 MiB (128 instances) >>>> L2: 512 MiB (128 instances) >>>> ``` >>>> >>>> This patch implements population of the sysfs cacheinfo structures >>>> for sun4v (systems with mdesc). The proper amount is now reflected in >>>> lscpu's output: >>>> >>>> ``` >>>> Caches (sum of all): >>>> L1d: 128 KiB (16 instances) >>>> L1i: 256 KiB (16 instances) >>>> L2: 8 MiB (2 instances) >>>> ``` >>>> >>>> Signed-off-by: Jan Engelhardt <jengelh@inai.de> >>>> --- >>>> arch/sparc/include/asm/cpudata_64.h | 8 +++- >>>> arch/sparc/kernel/mdesc.c | 61 >>>> +++++++++++++++++++++++++++++ >>>> 2 files changed, 68 insertions(+), 1 deletion(-) >>>> >>>> diff --git a/arch/sparc/include/asm/cpudata_64.h >>>> b/arch/sparc/include/asm/cpudata_64.h >>>> index 056b3c0e7ef9..e28b841ffe23 100644 >>>> --- a/arch/sparc/include/asm/cpudata_64.h >>>> +++ b/arch/sparc/include/asm/cpudata_64.h >>>> @@ -18,13 +18,19 @@ typedef struct { >>>> unsigned int irq0_irqs; >>>> unsigned int __pad2; >>>> - /* Dcache line 2, rarely used */ >>>> + /* Dcache line 2+3, rarely used */ >>>> unsigned int dcache_size; >>>> unsigned int dcache_line_size; >>>> + unsigned int dcache_assoc; >>>> + unsigned int dcache_id; >>>> unsigned int icache_size; >>>> unsigned int icache_line_size; >>>> + unsigned int icache_assoc; >>>> + unsigned int icache_id; >>>> unsigned int ecache_size; >>>> unsigned int ecache_line_size; >>>> + unsigned int ecache_assoc; >>>> + unsigned int ecache_id; >>>> unsigned short sock_id; /* physical package */ >>>> unsigned short core_id; >>>> unsigned short max_cache_id; /* groupings of highest >>>> shared cache */ >>>> diff --git a/arch/sparc/kernel/mdesc.c b/arch/sparc/kernel/mdesc.c >>>> index 23b51a32e96e..029d9d812074 100644 >>>> --- a/arch/sparc/kernel/mdesc.c >>>> +++ b/arch/sparc/kernel/mdesc.c >>>> @@ -818,6 +818,7 @@ static void fill_in_one_cache(cpuinfo_sparc *c, >>>> struct mdesc_handle *hp, u64 mp) >>>> const u64 *level = mdesc_get_property(hp, mp, "level", NULL); >>>> const u64 *size = mdesc_get_property(hp, mp, "size", NULL); >>>> const u64 *line_size = mdesc_get_property(hp, mp, >>>> "line-size", NULL); >>>> + const u64 *assoc = mdesc_get_property(hp, mp, "associativity", >>>> NULL); >>>> const char *type; >>>> int type_len; >>>> @@ -828,15 +829,21 @@ static void fill_in_one_cache(cpuinfo_sparc >>>> *c, struct mdesc_handle *hp, u64 mp) >>>> if (of_find_in_proplist(type, "instn", type_len)) { >>>> c->icache_size = *size; >>>> c->icache_line_size = *line_size; >>>> + c->icache_assoc = assoc ? *assoc : 0; >>>> + c->icache_id = mp; >>>> } else if (of_find_in_proplist(type, "data", type_len)) { >>>> c->dcache_size = *size; >>>> c->dcache_line_size = *line_size; >>>> + c->dcache_assoc = assoc ? *assoc : 0; >>>> + c->dcache_id = mp; >>>> } >>>> break; >>>> case 2: >>>> c->ecache_size = *size; >>>> c->ecache_line_size = *line_size; >>>> + c->ecache_assoc = assoc ? *assoc : 0; >>>> + c->ecache_id = mp; >>>> break; >>>> default: >>>> @@ -1251,6 +1258,60 @@ void mdesc_fill_in_cpu_data(cpumask_t *mask) >>>> smp_fill_in_sib_core_maps(); >>>> } >>>> +int init_cache_level(unsigned int cpu) >>>> +{ >>>> + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); >>>> + i->num_levels = 2; >>>> + i->num_leaves = 3; >>>> + return 0; >>>> +} >>>> + >>>> +int populate_cache_leaves(unsigned int cpu) >>>> +{ >>>> + struct cacheinfo *leaf = get_cpu_cacheinfo(cpu)->info_list; >>>> + cpuinfo_sparc *cs = &cpu_data(cpu); >>>> + >>>> + leaf->id = cs->icache_id; >>>> + leaf->attributes = CACHE_ID; >>>> + leaf->level = 1; >>>> + leaf->type = CACHE_TYPE_INST; >>>> + leaf->coherency_line_size = cs->icache_line_size; >>>> + leaf->ways_of_associativity = cs->icache_assoc; >>>> + leaf->size = cs->icache_size; >>>> + leaf->priv = cs; >>>> + if (cs->icache_line_size > 0 && cs->icache_assoc > 0) >>>> + leaf->number_of_sets = cs->icache_size / >>>> cs->icache_line_size / >>>> + cs->icache_assoc; >>>> + ++leaf; >>>> + >>>> + leaf->id = cs->dcache_id; >>>> + leaf->attributes = CACHE_ID; >>>> + leaf->level = 1; >>>> + leaf->type = CACHE_TYPE_DATA; >>>> + leaf->coherency_line_size = cs->dcache_line_size; >>>> + leaf->ways_of_associativity = cs->dcache_assoc; >>>> + leaf->size = cs->dcache_size; >>>> + leaf->priv = cs; >>>> + if (cs->dcache_line_size > 0 && cs->dcache_assoc > 0) >>>> + leaf->number_of_sets = cs->dcache_size / >>>> cs->dcache_line_size / >>>> + cs->dcache_assoc; >>>> + ++leaf; >>>> + >>>> + leaf->id = cs->ecache_id; >>>> + leaf->attributes = CACHE_ID; >>>> + leaf->level = 2; >>>> + leaf->type = CACHE_TYPE_UNIFIED; >>>> + leaf->coherency_line_size = cs->ecache_line_size; >>>> + leaf->ways_of_associativity = cs->ecache_assoc; >>>> + leaf->size = cs->ecache_size; >>>> + leaf->priv = cs; >>>> + if (cs->ecache_line_size > 0 && cs->ecache_assoc > 0) >>>> + leaf->number_of_sets = cs->ecache_size / >>>> cs->ecache_line_size / >>>> + cs->ecache_assoc; >>>> + >>>> + return 0; >>>> +} >>>> + >>>> /* mdesc_open() - Grab a reference to mdesc_handle when >>>> /dev/mdesc is >>>> * opened. Hold this reference until /dev/mdesc is closed to ensure >>>> * mdesc data structure is not released underneath us. Store the >> > I’ve applied the patch to a dual‑socket SPARC S7‑2 (16 cores total, > 128 threads) and wanted to share the resulting lscpu output, since it > clarifies what the patch fixes and what still needs work for 3‑level > parts. > > Before the patch: > > L1d: 2 MiB (128 instances) > L1i: 2 MiB (128 instances) > L2: 32 MiB (128 instances) > > After the patch: > > L1d: 256 KiB (16 instances) > L1i: 256 KiB (16 instances) > L2: 2 MiB (8 instances) > > A) The L1 reporting is now correct. Each of the 16 cores has a private > 16 KB L1I and 16 KB L1D, so 256 KiB in 16 instances is exactly right. > The per‑thread inflation is gone for L1, and the sharing/instance > counts are sensible. The generic leaf->id grouping is clearly doing > its job. > > * B) L2 is only half‑reported on S7: This may be true for S7, T7, > and T8 CPUs. > > For the L2 split (On S7): > > L2D: 256 KB shared by every 2 cores -> 8 instances × 256 KB = 2 > MiB (matches the output) > > L2I: 256 KB shared by every 4 cores ->4 instances × 256 KB = 1 > MiB (missing) > > So the total L2 on this box should be 3 MiB across 12 instances , or > shown as separate L2D/L2I lines. It looks like MDESC reports the L2I > and L2D nodes separately, and the current case 2: overwrites one with > the other in ecache_*. Supporting S7 properly would need either > separate storage for L2I/L2D or a way to handle multiple level‑2 nodes. > > * C) Need "level 3" cache details for (useful for T4, T5, S7, T7, > T8). Perhaps in revised patch? > > As expected, the S7’s 16 MB per‑socket L3 (32 MiB total, 2 instances > on this box) does not appear at all. init_cache_level() hardcodes > num_levels = 2 / num_leaves = 3, and fill_in_one_cache() has no case > 3:, so the MDESC level‑3 node is dropped in default. > > Adding an L3 leaf may need? > > l3_* fields in cpuinfo_sparc, > > a case 3: in fill_in_one_cache(), > > num_levels = 3 / num_leaves = 4 in init_cache_level(), > > a 4th leaf in populate_cache_leaves(). > > For T7‑1/T8‑1 this would surface their 64 MiB per‑socket L3; for S7‑2 > it would show 32 MiB in 2 instances (16 MiB per cpu). The T5240 result > looks correct because that machine is 2‑level only, so the missing > case 3: doesn’t show up there. > > Summary: > > The patch is an improvement but needs more work. It fixes the L1 (and > L2D) inflation on S7‑2. To make it complete for the 3‑level SPARC > parts, it needs L2I handling and an L3 leaf. It would be great to > have L3 cache details shown via lscpu as well. > > > Tested-By: Tony Rodriguez <unixpro1970@gmail.com> > > > Regards, > > Tony > Corrected typos in my summary and changed point C to be "Perhaps in a revised patch?" Tony ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH] sparc: populate sysfs cache topology information on sun4v 2026-10-18 22:27 [PATCH] sparc: populate sysfs cache topology information on sun4v Jan Engelhardt 2026-10-19 0:16 ` Tony Rodriguez @ 2026-10-19 9:49 ` Stian Halseth 1 sibling, 0 replies; 6+ messages in thread From: Stian Halseth @ 2026-10-19 9:49 UTC (permalink / raw) To: Jan Engelhardt, davem; +Cc: sparclinux, linux-kernel, John Paul Adrian Glaubitz [-- Attachment #1: Type: text/plain, Size: 2255 bytes --] Hi Jan, thanks for looking into this! On Mon, 2026-10-19 at 00:27 +0200, Jan Engelhardt wrote: > +int init_cache_level(unsigned int cpu) > +{ > + struct cpu_cacheinfo *i = get_cpu_cacheinfo(cpu); > + i->num_levels = 2; > + i->num_leaves = 3; Using the MD node as the cache id with CACHE_ID set looks to me like the right way to do it. I tried it on my T4-1 and V240 and have a few comments. mdesc.c is also built for sun4u and there the new *_id fields are never filled in and stay 0, so both CPUs end up sharing every cache. On my V240 lscpu goes from 128K L1d in 2 instances to 64K in 1, and the same for L1i and L2. A tlb_type == hypervisor check here, like the one in setup_per_cpu_areas(), and -ENOENT otherwise puts it back to how it is today. I tested that too. The fixed 2 levels / 3 leaves also only fits T1-T3. On the T4-1 L1 and L2 come out right now (16K and 128K per core, 8 instances), but the 4M L3 shared by all strands is missing. I dumped the cache nodes from /dev/mdesc on my T4-1 and T7-1: T4: L1i/L1d per core, L2 128K per core, L3 4M shared by all M7: L1i/L1d per core, L2 data per 2 cores + L2 instn per 4 cores (both level 2), L3 8M per 4 cores On M7 the L2 you get is whichever level 2 node fill_in_one_cache() hits last (data here), labelled Unified. That's what Tony saw on his S7 too. The missing L3 isn't just cosmetic either. The scheduler, sched_ext and the page allocator use the last leaf as the LLC, so the T4 would end up with a per-core 128K L2 as its LLC. Maybe it's simpler to just walk the MD directly in init_cache_level() and populate_cache_leaves(), following the same arcs as fill_in_one_cpu(), and add one leaf per cache node? Then you get the split L2 and the L3 for free, and cpuinfo_sparc doesn't have to grow. Tony, about your first list: CACHE_ID is right, it's the flag that tells the generic code leaf->id is valid. I built the T4 kernel without it as well, and then nothing shows up at all, cacheinfo just says "Failed to find cpu0 device node" and gives up. The functions override the __weak ones in drivers/base/cacheinfo.c, so they have to stay non-static. The L2 split and the L3 you found on the S7 are real though. /Stian [-- Attachment #2: This is a digitally signed message part --] [-- Type: application/pgp-signature, Size: 228 bytes --] ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2026-10-19 9:49 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
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2026-10-18 22:27 [PATCH] sparc: populate sysfs cache topology information on sun4v Jan Engelhardt
2026-10-19 0:16 ` Tony Rodriguez
2026-10-19 0:37 ` Tony Rodriguez
2026-10-19 2:32 ` Tony Rodriguez
[not found] ` <c7d7a96c-feb9-4676-8cc2-73529e8324ef@gmail.com>
2026-10-19 2:42 ` Tony Rodriguez
2026-10-19 9:49 ` Stian Halseth
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