* [PATCH v9 0/2] riscv: rtc: sophgo: add rtc support for CV1800 @ 2024-04-28 6:08 Jingbao Qiu 2024-04-28 6:08 ` [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Jingbao Qiu 2024-04-28 6:08 ` [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Jingbao Qiu 0 siblings, 2 replies; 5+ messages in thread From: Jingbao Qiu @ 2024-04-28 6:08 UTC (permalink / raw) To: alexandre.belloni, robh, krzysztof.kozlowski+dt, conor+dt, unicorn_wang, inochiama, paul.walmsley, palmer, aou Cc: dlan, devicetree, linux-kernel, linux-riscv, linux-rtc, Jingbao Qiu Real Time Clock (RTC) is an independently powered module within the chip, which includes a 32KHz oscillator and a Power On Reset/POR submodule. It can be used for time display and timed alarm generation. Power On Reset/POR submodule only using register resources so it should be empty. The 32KHz oscillator only provides pulses for RTC in hardware. Changes since v8: - delete unused macros - using 0/1 instead of the DISABLE/ENABLE macro - pass in the correct pointer when applying for IRQ - convert the incoming pointer into an appropriate structure pointer in the irq handler v8: https://lore.kernel.org/all/20240204044143.415915-1-qiujingbao.dlmu@gmail.com/ Changes since v7: - pass checkpatch.pl --strict - using u32 replace uint32 - using devm_kzalloc(*) replace devm_kzalloc(sizeof()) - sort header files alphabetically - delete unnecessary header files - fix wrap error - drop dependent description - using hardware automatic calibration replace software calibration. see documentation 197 page v7: https://lore.kernel.org/all/20240122080500.2621-1-qiujingbao.dlmu@gmail.com/ documentation: https://github.com/milkv-duo/duo-files/blob/main/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf Changes since v6: - completely delete POR dt node - remove syscon tag - use devm_regmap_init_mmio() replace syscon_node_to_regmap v6: https://lore.kernel.org/all/20240115160600.5444-1-qiujingbao.dlmu@gmail.com/ Changes since v5: - remove unnecessary lock - fix cv1800_rtc_alarm_irq_enable() - remove duplicate checks - using alrm->enabled instead of unconditionally enabling - remove disable alarms on probe - using rtc_update_irq() replace mess of alarm - remove leak clk - useing devm_rtc_allocate_device() and devm_rtc_register_device() instead old way - add judgment for rtc_enable_sec_counter() - add POR nodes in DTS. This POR device shares the register region with the RTC device v5: https://lore.kernel.org/all/20240108072253.30183-1-qiujingbao.dlmu@gmail.com/ Changes since v4: - remove POR dt-bindings because it empty - remove MFD dt-bindings because SoC does not have MFDs - add syscon attribute to share registers with POR v4: https://lore.kernel.org/all/20231229090643.116575-1-qiujingbao.dlmu@gmail.com/ Changes since v3: - temporarily not submitting RTC driver code waiting for communication with IC designer - add MFD dt-bindings - add POR dt-bindings v3: https://lore.kernel.org/all/20231226100431.331616-1-qiujingbao.dlmu@gmail.com/ Changes since v2: - add mfd support for CV1800 - add rtc to mfd - using regmap replace iomap - merge register address in dts v2: https://lore.kernel.org/lkml/20231217110952.78784-1-qiujingbao.dlmu@gmail.com/ Changes since v1 - fix duplicate names in subject - using RTC replace RTC controller - improve the properties of dt-bindings - using `unevaluatedProperties` replace `additionalProperties` - dt-bindings passed the test - using `devm_platform_ioremap_resource()` replace `platform_get_resource()` and `devm_ioremap_resource()` - fix random order of the code - fix wrong wrapping of the `devm_request_irq()` and map the flag with dts - using devm_clk_get_enabled replace `devm_clk_get()` and `clk_prepare_enable()` - fix return style - add rtc clock calibration function - use spinlock when write register on read/set time v1: https://lore.kernel.org/lkml/20231121094642.2973795-1-qiujingbao.dlmu@gmail.com/ Jingbao Qiu (2): dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC rtc: sophgo: add rtc support for Sophgo CV1800 SoC .../bindings/rtc/sophgo,cv1800-rtc.yaml | 53 ++++ drivers/rtc/Kconfig | 10 + drivers/rtc/Makefile | 1 + drivers/rtc/rtc-cv1800.c | 240 ++++++++++++++++++ 4 files changed, 304 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml create mode 100644 drivers/rtc/rtc-cv1800.c base-commit: 1c431b92e21bcbfc374f97d801840c1df47e3d6b -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC 2024-04-28 6:08 [PATCH v9 0/2] riscv: rtc: sophgo: add rtc support for CV1800 Jingbao Qiu @ 2024-04-28 6:08 ` Jingbao Qiu 2025-02-11 21:17 ` Alexander Sverdlin 2024-04-28 6:08 ` [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Jingbao Qiu 1 sibling, 1 reply; 5+ messages in thread From: Jingbao Qiu @ 2024-04-28 6:08 UTC (permalink / raw) To: alexandre.belloni, robh, krzysztof.kozlowski+dt, conor+dt, unicorn_wang, inochiama, paul.walmsley, palmer, aou Cc: dlan, devicetree, linux-kernel, linux-riscv, linux-rtc, Jingbao Qiu, Krzysztof Kozlowski Add RTC devicetree binding for Sophgo CV1800 SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> --- .../bindings/rtc/sophgo,cv1800-rtc.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml new file mode 100644 index 000000000000..b36b51a69166 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/sophgo,cv1800-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + Real Time Clock (RTC) is an independently powered module + within the chip, which includes a 32KHz oscillator and a + Power On Reset/POR submodule. It can be used for time display + and timed alarm generation. In addition, the hardware state + machine provides triggering and timing control for chip + power on, off, and reset. + +maintainers: + - Jingbao Qiu <qiujingbao.dlmu@gmail.com> + +allOf: + - $ref: rtc.yaml# + +properties: + compatible: + const: sophgo,cv1800-rtc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + rtc@5025000 { + compatible = "sophgo,cv1800-rtc"; + reg = <0x5025000 0x2000>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + }; -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC 2024-04-28 6:08 ` [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Jingbao Qiu @ 2025-02-11 21:17 ` Alexander Sverdlin 0 siblings, 0 replies; 5+ messages in thread From: Alexander Sverdlin @ 2025-02-11 21:17 UTC (permalink / raw) To: Jingbao Qiu, alexandre.belloni, robh, krzysztof.kozlowski+dt, conor+dt, unicorn_wang, inochiama, paul.walmsley, palmer, aou Cc: dlan, devicetree, linux-kernel, linux-riscv, linux-rtc, Krzysztof Kozlowski Thanks for your patch Jingbao! On Sun, 2024-04-28 at 14:08 +0800, Jingbao Qiu wrote: > Add RTC devicetree binding for Sophgo CV1800 SoC. > > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> Verified against SG2000 TRM [1], the bindings make sense to me. Reviewed-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> [1] https://github.com/sophgo/sophgo-doc/releases/download/sg2000-trm-v1.01/sg2000_trm_en.pdf --- > .../bindings/rtc/sophgo,cv1800-rtc.yaml | 53 +++++++++++++++++++ > 1 file changed, 53 insertions(+) > create mode 100644 Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml > > diff --git a/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml > new file mode 100644 > index 000000000000..b36b51a69166 > --- /dev/null > +++ b/Documentation/devicetree/bindings/rtc/sophgo,cv1800-rtc.yaml > @@ -0,0 +1,53 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/rtc/sophgo,cv1800-rtc.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Real Time Clock of the Sophgo CV1800 SoC > + > +description: > + Real Time Clock (RTC) is an independently powered module > + within the chip, which includes a 32KHz oscillator and a > + Power On Reset/POR submodule. It can be used for time display > + and timed alarm generation. In addition, the hardware state > + machine provides triggering and timing control for chip > + power on, off, and reset. > + > +maintainers: > + - Jingbao Qiu <qiujingbao.dlmu@gmail.com> > + > +allOf: > + - $ref: rtc.yaml# > + > +properties: > + compatible: > + const: sophgo,cv1800-rtc > + > + reg: > + maxItems: 1 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > +required: > + - compatible > + - reg > + - interrupts > + - clocks > + > +unevaluatedProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + > + rtc@5025000 { > + compatible = "sophgo,cv1800-rtc"; > + reg = <0x5025000 0x2000>; > + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + }; -- Alexander Sverdlin. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC 2024-04-28 6:08 [PATCH v9 0/2] riscv: rtc: sophgo: add rtc support for CV1800 Jingbao Qiu 2024-04-28 6:08 ` [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Jingbao Qiu @ 2024-04-28 6:08 ` Jingbao Qiu 2025-02-11 23:47 ` Alexander Sverdlin 1 sibling, 1 reply; 5+ messages in thread From: Jingbao Qiu @ 2024-04-28 6:08 UTC (permalink / raw) To: alexandre.belloni, robh, krzysztof.kozlowski+dt, conor+dt, unicorn_wang, inochiama, paul.walmsley, palmer, aou Cc: dlan, devicetree, linux-kernel, linux-riscv, linux-rtc, Jingbao Qiu Implement the RTC driver for CV1800, which able to provide time alarm. Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> --- drivers/rtc/Kconfig | 10 ++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-cv1800.c | 240 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 251 insertions(+) create mode 100644 drivers/rtc/rtc-cv1800.c diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 2a95b05982ad..b7746ca22b94 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1138,6 +1138,16 @@ config RTC_DRV_DS2404 This driver can also be built as a module. If so, the module will be called rtc-ds2404. +config RTC_DRV_CV1800 + tristate "Sophgo CV1800 RTC" + depends on ARCH_SOPHGO || COMPILE_TEST + help + If you say yes here you get support the RTC driver + for Sophgo CV1800 chip. + + This driver can also be built as a module.If so, the + module will be called rtc-cv1800. + config RTC_DRV_DA9052 tristate "Dialog DA9052/DA9053 RTC" depends on PMIC_DA9052 diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 3004e372f25f..a0861c0f3c89 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -42,6 +42,7 @@ obj-$(CONFIG_RTC_DRV_CADENCE) += rtc-cadence.o obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o obj-$(CONFIG_RTC_DRV_CPCAP) += rtc-cpcap.o obj-$(CONFIG_RTC_DRV_CROS_EC) += rtc-cros-ec.o +obj-$(CONFIG_RTC_DRV_CV1800) += rtc-cv1800.o obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o diff --git a/drivers/rtc/rtc-cv1800.c b/drivers/rtc/rtc-cv1800.c new file mode 100644 index 000000000000..f975b169077a --- /dev/null +++ b/drivers/rtc/rtc-cv1800.c @@ -0,0 +1,240 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * rtc-cv1800.c: RTC driver for Sophgo cv1800 RTC + * + * Author: Jingbao Qiu <qiujingbao.dlmu@gmail.com> + */ + +#include <linux/clk.h> +#include <linux/irq.h> +#include <linux/kernel.h> +#include <linux/module.h> +#include <linux/of.h> +#include <linux/platform_device.h> +#include <linux/regmap.h> +#include <linux/rtc.h> + +#define CTRL 0x08 +#define ANA_CALIB 0x1000 +#define SEC_PULSE_GEN 0x1004 +#define ALARM_TIME 0x1008 +#define ALARM_ENABLE 0x100C +#define SET_SEC_CNTR_VAL 0x1010 +#define SET_SEC_CNTR_TRIG 0x1014 +#define SEC_CNTR_VAL 0x1018 + +/* + * When in VDDBKUP domain, this MACRO register + * does not power down + */ +#define MACRO_RO_T 0x14A8 +#define MACRO_RG_SET_T 0x1498 + +#define CTRL_MODE_MASK BIT(10) +#define CTRL_MODE_OSC32K 0x00UL +#define ALARM_ENABLE_MASK BIT(0) +#define SET_SEC_CNTR_VAL_INIT GENMASK(29, 28) +#define SEC_PULSE_SEL_INNER BIT(31) +#define SEC_PULSE_GEN_SEL_MASK GENMASK(30, 0) +#define CALIB_SEL_FTUNE_MASK GENMASK(30, 0) +#define CALIB_SEL_FTUNE_INNER 0x00UL + +struct cv1800_rtc_priv { + struct rtc_device *rtc_dev; + struct regmap *rtc_map; + struct clk *clk; + int irq; +}; + +static const struct regmap_config cv1800_rtc_regmap_config = { + .reg_bits = 32, + .val_bits = 32, + .reg_stride = 4, +}; + +static int cv1800_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) +{ + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); + + regmap_write(info->rtc_map, ALARM_ENABLE, enabled); + + return 0; +} + +static int cv1800_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) +{ + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); + unsigned long alarm_time; + + alarm_time = rtc_tm_to_time64(&alrm->time); + + cv1800_rtc_alarm_irq_enable(dev, 0); + + regmap_write(info->rtc_map, ALARM_TIME, alarm_time); + + cv1800_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static int cv1800_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) +{ + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); + u32 enabled; + u32 time; + + regmap_read(info->rtc_map, ALARM_ENABLE, &enabled); + + alarm->enabled = enabled & ALARM_ENABLE_MASK; + + regmap_read(info->rtc_map, ALARM_TIME, &time); + + rtc_time64_to_tm(time, &alarm->time); + + return 0; +} + +static void rtc_enable_sec_counter(struct cv1800_rtc_priv *info) +{ + u32 sec_ro_t; + u32 sec; + + /* select inner sec pulse */ + regmap_update_bits(info->rtc_map, SEC_PULSE_GEN, + (u32)(~SEC_PULSE_GEN_SEL_MASK), + (u32)(~SEC_PULSE_SEL_INNER)); + + regmap_update_bits(info->rtc_map, ANA_CALIB, + (u32)(~CALIB_SEL_FTUNE_MASK), + CALIB_SEL_FTUNE_INNER); + + sec = SET_SEC_CNTR_VAL_INIT; + + /* load from MACRO register */ + regmap_read(info->rtc_map, MACRO_RO_T, &sec_ro_t); + if (sec_ro_t > (SET_SEC_CNTR_VAL_INIT)) + sec = sec_ro_t; + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); +} + +static int cv1800_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); + u32 sec; + + regmap_read(info->rtc_map, SEC_CNTR_VAL, &sec); + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int cv1800_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); + unsigned long sec; + + sec = rtc_tm_to_time64(tm); + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); + + regmap_write(info->rtc_map, MACRO_RG_SET_T, sec); + + return 0; +} + +static irqreturn_t cv1800_rtc_irq_handler(int irq, void *dev_id) +{ + struct cv1800_rtc_priv *info = dev_id; + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + + regmap_write(info->rtc_map, ALARM_ENABLE, 0); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops cv1800_rtc_ops = { + .read_time = cv1800_rtc_read_time, + .set_time = cv1800_rtc_set_time, + .read_alarm = cv1800_rtc_read_alarm, + .set_alarm = cv1800_rtc_set_alarm, + .alarm_irq_enable = cv1800_rtc_alarm_irq_enable, +}; + +static int cv1800_rtc_probe(struct platform_device *pdev) +{ + struct cv1800_rtc_priv *rtc; + u32 ctrl_val; + void __iomem *base; + int ret; + + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + rtc->rtc_map = devm_regmap_init_mmio(&pdev->dev, base, + &cv1800_rtc_regmap_config); + if (IS_ERR(rtc->rtc_map)) + return PTR_ERR(rtc->rtc_map); + + rtc->irq = platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->clk = devm_clk_get_enabled(&pdev->dev, NULL); + if (IS_ERR(rtc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), + "clk not found\n"); + + platform_set_drvdata(pdev, rtc); + + device_init_wakeup(&pdev->dev, 1); + + rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + rtc->rtc_dev->ops = &cv1800_rtc_ops; + rtc->rtc_dev->range_max = U32_MAX; + + ret = devm_request_irq(&pdev->dev, rtc->irq, cv1800_rtc_irq_handler, + IRQF_TRIGGER_HIGH, "rtc alarm", rtc); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "cannot register interrupt handler\n"); + + regmap_read(rtc->rtc_map, CTRL, &ctrl_val); + ctrl_val &= CTRL_MODE_MASK; + + if (ctrl_val == CTRL_MODE_OSC32K) + rtc_enable_sec_counter(rtc); + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static const struct of_device_id cv1800_dt_ids[] = { + { .compatible = "sophgo,cv1800-rtc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(of, cv1800_dt_ids); + +static struct platform_driver cv1800_rtc_driver = { + .driver = { + .name = "sophgo-cv1800-rtc", + .of_match_table = cv1800_dt_ids, + }, + .probe = cv1800_rtc_probe, +}; + +module_platform_driver(cv1800_rtc_driver); +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 RTC Driver"); +MODULE_LICENSE("GPL"); -- 2.25.1 ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC 2024-04-28 6:08 ` [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Jingbao Qiu @ 2025-02-11 23:47 ` Alexander Sverdlin 0 siblings, 0 replies; 5+ messages in thread From: Alexander Sverdlin @ 2025-02-11 23:47 UTC (permalink / raw) To: Jingbao Qiu, alexandre.belloni, robh, krzysztof.kozlowski+dt, conor+dt, unicorn_wang, inochiama, paul.walmsley, palmer, aou Cc: dlan, devicetree, linux-kernel, linux-riscv, linux-rtc Thanks for you patch Jingbao! On Sun, 2024-04-28 at 14:08 +0800, Jingbao Qiu wrote: > Implement the RTC driver for CV1800, which able to provide time alarm. > > Signed-off-by: Jingbao Qiu <qiujingbao.dlmu@gmail.com> I've tried time read/set on SG2000 SoC (Milk-V Duo Module 01 EVB), however the time set remains unchanged. Milk-V Duo Module 01 schematics shows 32768Hz oscillator present. What HW have you tested the driver on? Do you have an idea what could be the problem on SG2000? > --- > drivers/rtc/Kconfig | 10 ++ > drivers/rtc/Makefile | 1 + > drivers/rtc/rtc-cv1800.c | 240 +++++++++++++++++++++++++++++++++++++++ > 3 files changed, 251 insertions(+) > create mode 100644 drivers/rtc/rtc-cv1800.c > > diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig > index 2a95b05982ad..b7746ca22b94 100644 > --- a/drivers/rtc/Kconfig > +++ b/drivers/rtc/Kconfig > @@ -1138,6 +1138,16 @@ config RTC_DRV_DS2404 > This driver can also be built as a module. If so, the module > will be called rtc-ds2404. > > +config RTC_DRV_CV1800 > + tristate "Sophgo CV1800 RTC" > + depends on ARCH_SOPHGO || COMPILE_TEST > + help > + If you say yes here you get support the RTC driver > + for Sophgo CV1800 chip. > + > + This driver can also be built as a module.If so, the > + module will be called rtc-cv1800. > + > config RTC_DRV_DA9052 > tristate "Dialog DA9052/DA9053 RTC" > depends on PMIC_DA9052 > diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile > index 3004e372f25f..a0861c0f3c89 100644 > --- a/drivers/rtc/Makefile > +++ b/drivers/rtc/Makefile > @@ -42,6 +42,7 @@ obj-$(CONFIG_RTC_DRV_CADENCE) += rtc-cadence.o > obj-$(CONFIG_RTC_DRV_CMOS) += rtc-cmos.o > obj-$(CONFIG_RTC_DRV_CPCAP) += rtc-cpcap.o > obj-$(CONFIG_RTC_DRV_CROS_EC) += rtc-cros-ec.o > +obj-$(CONFIG_RTC_DRV_CV1800) += rtc-cv1800.o > obj-$(CONFIG_RTC_DRV_DA9052) += rtc-da9052.o > obj-$(CONFIG_RTC_DRV_DA9055) += rtc-da9055.o > obj-$(CONFIG_RTC_DRV_DA9063) += rtc-da9063.o > diff --git a/drivers/rtc/rtc-cv1800.c b/drivers/rtc/rtc-cv1800.c > new file mode 100644 > index 000000000000..f975b169077a > --- /dev/null > +++ b/drivers/rtc/rtc-cv1800.c > @@ -0,0 +1,240 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * rtc-cv1800.c: RTC driver for Sophgo cv1800 RTC > + * > + * Author: Jingbao Qiu <qiujingbao.dlmu@gmail.com> > + */ > + > +#include <linux/clk.h> > +#include <linux/irq.h> > +#include <linux/kernel.h> > +#include <linux/module.h> > +#include <linux/of.h> > +#include <linux/platform_device.h> > +#include <linux/regmap.h> > +#include <linux/rtc.h> > + > +#define CTRL 0x08 > +#define ANA_CALIB 0x1000 > +#define SEC_PULSE_GEN 0x1004 > +#define ALARM_TIME 0x1008 > +#define ALARM_ENABLE 0x100C > +#define SET_SEC_CNTR_VAL 0x1010 > +#define SET_SEC_CNTR_TRIG 0x1014 > +#define SEC_CNTR_VAL 0x1018 > + > +/* > + * When in VDDBKUP domain, this MACRO register > + * does not power down > + */ > +#define MACRO_RO_T 0x14A8 > +#define MACRO_RG_SET_T 0x1498 > + > +#define CTRL_MODE_MASK BIT(10) > +#define CTRL_MODE_OSC32K 0x00UL > +#define ALARM_ENABLE_MASK BIT(0) > +#define SET_SEC_CNTR_VAL_INIT GENMASK(29, 28) > +#define SEC_PULSE_SEL_INNER BIT(31) > +#define SEC_PULSE_GEN_SEL_MASK GENMASK(30, 0) > +#define CALIB_SEL_FTUNE_MASK GENMASK(30, 0) > +#define CALIB_SEL_FTUNE_INNER 0x00UL > + > +struct cv1800_rtc_priv { > + struct rtc_device *rtc_dev; > + struct regmap *rtc_map; > + struct clk *clk; > + int irq; > +}; > + > +static const struct regmap_config cv1800_rtc_regmap_config = { > + .reg_bits = 32, > + .val_bits = 32, > + .reg_stride = 4, > +}; > + > +static int cv1800_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) > +{ > + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); > + > + regmap_write(info->rtc_map, ALARM_ENABLE, enabled); > + > + return 0; > +} > + > +static int cv1800_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm) > +{ > + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); > + unsigned long alarm_time; > + > + alarm_time = rtc_tm_to_time64(&alrm->time); > + > + cv1800_rtc_alarm_irq_enable(dev, 0); > + > + regmap_write(info->rtc_map, ALARM_TIME, alarm_time); > + > + cv1800_rtc_alarm_irq_enable(dev, alrm->enabled); > + > + return 0; > +} > + > +static int cv1800_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) > +{ > + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); > + u32 enabled; > + u32 time; > + > + regmap_read(info->rtc_map, ALARM_ENABLE, &enabled); > + > + alarm->enabled = enabled & ALARM_ENABLE_MASK; > + > + regmap_read(info->rtc_map, ALARM_TIME, &time); > + > + rtc_time64_to_tm(time, &alarm->time); > + > + return 0; > +} > + > +static void rtc_enable_sec_counter(struct cv1800_rtc_priv *info) > +{ > + u32 sec_ro_t; > + u32 sec; > + > + /* select inner sec pulse */ > + regmap_update_bits(info->rtc_map, SEC_PULSE_GEN, > + (u32)(~SEC_PULSE_GEN_SEL_MASK), > + (u32)(~SEC_PULSE_SEL_INNER)); > + > + regmap_update_bits(info->rtc_map, ANA_CALIB, > + (u32)(~CALIB_SEL_FTUNE_MASK), > + CALIB_SEL_FTUNE_INNER); > + > + sec = SET_SEC_CNTR_VAL_INIT; > + > + /* load from MACRO register */ > + regmap_read(info->rtc_map, MACRO_RO_T, &sec_ro_t); > + if (sec_ro_t > (SET_SEC_CNTR_VAL_INIT)) > + sec = sec_ro_t; > + > + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); > + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); > +} > + > +static int cv1800_rtc_read_time(struct device *dev, struct rtc_time *tm) > +{ > + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); > + u32 sec; > + > + regmap_read(info->rtc_map, SEC_CNTR_VAL, &sec); > + > + rtc_time64_to_tm(sec, tm); > + > + return 0; > +} > + > +static int cv1800_rtc_set_time(struct device *dev, struct rtc_time *tm) > +{ > + struct cv1800_rtc_priv *info = dev_get_drvdata(dev); > + unsigned long sec; > + > + sec = rtc_tm_to_time64(tm); > + > + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); > + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); > + > + regmap_write(info->rtc_map, MACRO_RG_SET_T, sec); > + > + return 0; > +} > + > +static irqreturn_t cv1800_rtc_irq_handler(int irq, void *dev_id) > +{ > + struct cv1800_rtc_priv *info = dev_id; > + > + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); > + > + regmap_write(info->rtc_map, ALARM_ENABLE, 0); > + > + return IRQ_HANDLED; > +} > + > +static const struct rtc_class_ops cv1800_rtc_ops = { > + .read_time = cv1800_rtc_read_time, > + .set_time = cv1800_rtc_set_time, > + .read_alarm = cv1800_rtc_read_alarm, > + .set_alarm = cv1800_rtc_set_alarm, > + .alarm_irq_enable = cv1800_rtc_alarm_irq_enable, > +}; > + > +static int cv1800_rtc_probe(struct platform_device *pdev) > +{ > + struct cv1800_rtc_priv *rtc; > + u32 ctrl_val; > + void __iomem *base; > + int ret; > + > + rtc = devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); > + if (!rtc) > + return -ENOMEM; > + > + base = devm_platform_ioremap_resource(pdev, 0); > + if (IS_ERR(base)) > + return PTR_ERR(base); > + > + rtc->rtc_map = devm_regmap_init_mmio(&pdev->dev, base, > + &cv1800_rtc_regmap_config); > + if (IS_ERR(rtc->rtc_map)) > + return PTR_ERR(rtc->rtc_map); > + > + rtc->irq = platform_get_irq(pdev, 0); > + if (rtc->irq < 0) > + return rtc->irq; > + > + rtc->clk = devm_clk_get_enabled(&pdev->dev, NULL); > + if (IS_ERR(rtc->clk)) > + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), > + "clk not found\n"); > + > + platform_set_drvdata(pdev, rtc); > + > + device_init_wakeup(&pdev->dev, 1); > + > + rtc->rtc_dev = devm_rtc_allocate_device(&pdev->dev); > + if (IS_ERR(rtc->rtc_dev)) > + return PTR_ERR(rtc->rtc_dev); > + > + rtc->rtc_dev->ops = &cv1800_rtc_ops; > + rtc->rtc_dev->range_max = U32_MAX; > + > + ret = devm_request_irq(&pdev->dev, rtc->irq, cv1800_rtc_irq_handler, > + IRQF_TRIGGER_HIGH, "rtc alarm", rtc); > + if (ret) > + return dev_err_probe(&pdev->dev, ret, > + "cannot register interrupt handler\n"); > + > + regmap_read(rtc->rtc_map, CTRL, &ctrl_val); > + ctrl_val &= CTRL_MODE_MASK; > + > + if (ctrl_val == CTRL_MODE_OSC32K) > + rtc_enable_sec_counter(rtc); > + > + return devm_rtc_register_device(rtc->rtc_dev); > +} > + > +static const struct of_device_id cv1800_dt_ids[] = { > + { .compatible = "sophgo,cv1800-rtc" }, > + { /* sentinel */ }, > +}; > +MODULE_DEVICE_TABLE(of, cv1800_dt_ids); > + > +static struct platform_driver cv1800_rtc_driver = { > + .driver = { > + .name = "sophgo-cv1800-rtc", > + .of_match_table = cv1800_dt_ids, > + }, > + .probe = cv1800_rtc_probe, > +}; > + > +module_platform_driver(cv1800_rtc_driver); > +MODULE_AUTHOR("Jingbao Qiu"); > +MODULE_DESCRIPTION("Sophgo cv1800 RTC Driver"); > +MODULE_LICENSE("GPL"); -- Alexander Sverdlin. ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-02-11 23:47 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2024-04-28 6:08 [PATCH v9 0/2] riscv: rtc: sophgo: add rtc support for CV1800 Jingbao Qiu 2024-04-28 6:08 ` [PATCH v9 1/2] dt-bindings: rtc: sophgo: add RTC support for Sophgo CV1800 series SoC Jingbao Qiu 2025-02-11 21:17 ` Alexander Sverdlin 2024-04-28 6:08 ` [PATCH v9 2/2] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Jingbao Qiu 2025-02-11 23:47 ` Alexander Sverdlin
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