[PATCH 0/6] Add Additional algo mode for inline encryption

[PATCH 0/6] Add Additional algo mode for inline encryption

[Md Sadre Alam]

This series of patches add additional modes for inline encryption

This series of patches depends on [1] Add inline encryption support for dm-crypt

[1]: https://lore.kernel.org/all/b45d3b40-2587-04dc-9601-a9251dacf806@opensource.wdc.com/T/#ma01f08a941107217c93680fa25e96e8d406df790

These patches tested on IPQ9574 with eMMC ICE for raw partition
encryption/decryption.

e.g:

dmsetup create test-crypt --table '0 251904 crypt aes128-xts-plain64 a7f67ad520bd83b9725df6ebd76c3eeea7f67ad520bd83b9725df6ebd76c3eee 0 /dev/mmcblk0p27 0 1 inline_crypt'

dd if=/dev/urandom of=/tmp/data bs=1M count=1

dd if=/tmp/data of=/dev/mapper/test-crypt bs=1M count=1

dd of=/tmp/data1 if=/dev/mapper/test-crypt bs=1M count=1

dd of=/tmp/data2 if=/dev/mmcblk0p27 bs=1M count=1

md5sum /tmp/data*
b45d728bfb499b6de9b12c98fbb652dd  /tmp/data
b45d728bfb499b6de9b12c98fbb652dd  /tmp/data1
bc4107e19cf6fc012c5b997bdd3f0de4  /tmp/data2

dmsetup remove /dev/mapper/test-crypt

Md Sadre Alam (6):
  md: dm-crypt: Fix compilation issue
  md: dm-crypt: Set cc->iv_size to 4 bytes
  blk-crypto: Add additional algo modes for Inline encryption
  md: dm-crypt: Add additional algo modes for inline encryption
  mmc: cqhci: Add additional algo mode for inline encryption
  mmc: sdhci-msm: Add additional algo mode for inline encryption

 block/blk-crypto.c              | 18 +++++++++
 drivers/md/dm-crypt.c           | 26 ++++++-------
 drivers/mmc/host/cqhci-crypto.c | 12 ++++++
 drivers/mmc/host/sdhci-msm.c    | 10 +----
 drivers/soc/qcom/ice.c          | 65 ++++++++++++++++++++++++++++-----
 include/linux/blk-crypto.h      |  3 ++
 6 files changed, 103 insertions(+), 31 deletions(-)

-- 
2.34.1

[PATCH 1/6] md: dm-crypt: Fix compilation issue

[Md Sadre Alam]

Fix compilation issue due to inline encryption change.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/md/dm-crypt.c | 16 ++++------------
 1 file changed, 4 insertions(+), 12 deletions(-)

diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index eb59b02f9bf2..37add222b169 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -233,7 +233,6 @@ struct crypt_config {
 
 #ifdef CONFIG_BLK_INLINE_ENCRYPTION
 	enum blk_crypto_mode_num crypto_mode;
-	enum blk_crypto_key_type key_type;
 	struct blk_crypto_key *blk_key;
 #endif
 	u8 *authenc_key; /* space for keys in authenc() format (if used) */
@@ -2485,10 +2484,6 @@ static int crypt_select_inline_crypt_mode(struct dm_target *ti, char *cipher,
 
 	if (strcmp(cipher, "xts(aes)") == 0) {
 		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_256_XTS;
-		cc->key_type = BLK_CRYPTO_KEY_TYPE_STANDARD;
-	} else if (strcmp(cipher, "xts(paes)") == 0) {
-		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_256_XTS;
-		cc->key_type = BLK_CRYPTO_KEY_TYPE_HW_WRAPPED;
 	} else {
 		ti->error = "Invalid cipher for inline_crypt";
 		return -EINVAL;
@@ -2512,16 +2507,14 @@ static int crypt_prepare_inline_crypt_key(struct crypt_config *cc)
 	if (!cc->blk_key)
 		return -ENOMEM;
 
-	ret = blk_crypto_init_key(cc->blk_key, cc->key, cc->key_size,
-				  cc->key_type, cc->crypto_mode, cc->iv_size,
-				  cc->sector_size);
+	ret = blk_crypto_init_key(cc->blk_key, cc->key, cc->crypto_mode,
+				  cc->iv_size, cc->sector_size);
 	if (ret) {
 		DMERR("Failed to init inline encryption key");
 		goto bad_key;
 	}
 
-	ret = blk_crypto_start_using_key(cc->blk_key,
-					 bdev_get_queue(cc->dev->bdev));
+	ret = blk_crypto_start_using_key(cc->dev->bdev, cc->blk_key);
 	if (ret) {
 		DMERR("Failed to use inline encryption key");
 		goto bad_key;
@@ -2537,8 +2530,7 @@ static int crypt_prepare_inline_crypt_key(struct crypt_config *cc)
 static void crypt_destroy_inline_crypt_key(struct crypt_config *cc)
 {
 	if (cc->blk_key) {
-		blk_crypto_evict_key(bdev_get_queue(cc->dev->bdev),
-				     cc->blk_key);
+		blk_crypto_evict_key(cc->dev->bdev, cc->blk_key);
 		kfree_sensitive(cc->blk_key);
 		cc->blk_key = NULL;
 	}
-- 
2.34.1

[PATCH 2/6] md: dm-crypt: Set cc->iv_size to 4 bytes

[Md Sadre Alam]

Set cc->iv_size to 4 bytes instead of 8 bytes, since
this cc->iv_size is passing as data unit bytes to
blk_crypto_init_key(). Since CQHCI driver having
limitation for data unit bytes to 32-bit only.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/md/dm-crypt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index 37add222b169..c0257d961968 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -2490,7 +2490,7 @@ static int crypt_select_inline_crypt_mode(struct dm_target *ti, char *cipher,
 	}
 
 	if (ivmode == NULL || (strcmp(ivmode, "plain64") == 0)) {
-		cc->iv_size = 8;
+		cc->iv_size = 4;
 	} else {
 		ti->error = "Invalid IV mode for inline_crypt";
 		return -EINVAL;
-- 
2.34.1

Re: [PATCH 2/6] md: dm-crypt: Set cc->iv_size to 4 bytes

[Milan Broz]

On 7/30/24 1:58 PM, Md Sadre Alam wrote:
> Set cc->iv_size to 4 bytes instead of 8 bytes, since
> this cc->iv_size is passing as data unit bytes to
> blk_crypto_init_key(). Since CQHCI driver having
> limitation for data unit bytes to 32-bit only.

In dm-crypt, plain64 IV is defined as "little-endian 64bit IV"
and was introduced to fix security problem when 32bit "plain" IV
overflows and IV is reused.

In that case you can move ciphertext sector between places with
the same IV (but different offsets) and these will be still
correctly decrypted.

If I understand it correctly, this reintroduces the same problem here.
If you have 32bit only, just use "plain" and do not support plain64 here.

(In general, I do not understand why you are sending patches
for dm-crypt code that is clearly not upstream.
I hope this code will never be accepted.)

Milan

> 
> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
> ---
>   drivers/md/dm-crypt.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
> index 37add222b169..c0257d961968 100644
> --- a/drivers/md/dm-crypt.c
> +++ b/drivers/md/dm-crypt.c
> @@ -2490,7 +2490,7 @@ static int crypt_select_inline_crypt_mode(struct dm_target *ti, char *cipher,
>   	}
>   
>   	if (ivmode == NULL || (strcmp(ivmode, "plain64") == 0)) {
> -		cc->iv_size = 8;
> +		cc->iv_size = 4;
>   	} else {
>   		ti->error = "Invalid IV mode for inline_crypt";
>   		return -EINVAL;

Re: [PATCH 2/6] md: dm-crypt: Set cc->iv_size to 4 bytes

[Md Sadre Alam]

On 7/31/2024 6:11 PM, Milan Broz wrote:
> On 7/30/24 1:58 PM, Md Sadre Alam wrote:
>> Set cc->iv_size to 4 bytes instead of 8 bytes, since
>> this cc->iv_size is passing as data unit bytes to
>> blk_crypto_init_key(). Since CQHCI driver having
>> limitation for data unit bytes to 32-bit only.
> 
> In dm-crypt, plain64 IV is defined as "little-endian 64bit IV"
> and was introduced to fix security problem when 32bit "plain" IV
> overflows and IV is reused.
> 
> In that case you can move ciphertext sector between places with
> the same IV (but different offsets) and these will be still
> correctly decrypted.
> 
> If I understand it correctly, this reintroduces the same problem here.
> If you have 32bit only, just use "plain" and do not support plain64 here.
> 
> (In general, I do not understand why you are sending patches
> for dm-crypt code that is clearly not upstream.
> I hope this code will never be accepted.)

  Thanks for reviewing. As Mikulas suggested for
  new target driver for "inline-crypt". Will create
  new target driver and post it.

> 
> Milan
> 
>>
>> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
>> ---
>>   drivers/md/dm-crypt.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
>> index 37add222b169..c0257d961968 100644
>> --- a/drivers/md/dm-crypt.c
>> +++ b/drivers/md/dm-crypt.c
>> @@ -2490,7 +2490,7 @@ static int crypt_select_inline_crypt_mode(struct dm_target *ti, char *cipher,
>>       }
>>       if (ivmode == NULL || (strcmp(ivmode, "plain64") == 0)) {
>> -        cc->iv_size = 8;
>> +        cc->iv_size = 4;
>>       } else {
>>           ti->error = "Invalid IV mode for inline_crypt";
>>           return -EINVAL;
> 

[PATCH 3/6] blk-crypto: Add additional algo modes for Inline encryption

[Md Sadre Alam]

Add AES-XTS-128, AES-CBC-128, AES-CBC-256 algo mode support
in blk_crypto for inline encryption.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 block/blk-crypto.c         | 18 ++++++++++++++++++
 include/linux/blk-crypto.h |  3 +++
 2 files changed, 21 insertions(+)

diff --git a/block/blk-crypto.c b/block/blk-crypto.c
index 51b51d6b07f3..43dc34e17d6a 100644
--- a/block/blk-crypto.c
+++ b/block/blk-crypto.c
@@ -19,6 +19,12 @@
 #include "blk-crypto-internal.h"
 
 const struct blk_crypto_mode blk_crypto_modes[] = {
+	[BLK_ENCRYPTION_MODE_AES_128_XTS] = {
+		.name = "AES-128-XTS",
+		.cipher_str = "xts(aes)",
+		.keysize = 32,
+		.ivsize = 16,
+	},
 	[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
 		.name = "AES-256-XTS",
 		.cipher_str = "xts(aes)",
@@ -43,6 +49,18 @@ const struct blk_crypto_mode blk_crypto_modes[] = {
 		.keysize = 32,
 		.ivsize = 16,
 	},
+	[BLK_ENCRYPTION_MODE_AES_128_CBC] = {
+		.name = "AES-128-CBC",
+		.cipher_str = "cbc(aes)",
+		.keysize = 16,
+		.ivsize = 16,
+	},
+	[BLK_ENCRYPTION_MODE_AES_256_CBC] = {
+		.name = "AES-256-CBC",
+		.cipher_str = "cbc(aes)",
+		.keysize = 32,
+		.ivsize = 16,
+	},
 };
 
 /*
diff --git a/include/linux/blk-crypto.h b/include/linux/blk-crypto.h
index 5e5822c18ee4..da503a05c5f6 100644
--- a/include/linux/blk-crypto.h
+++ b/include/linux/blk-crypto.h
@@ -10,10 +10,13 @@
 
 enum blk_crypto_mode_num {
 	BLK_ENCRYPTION_MODE_INVALID,
+	BLK_ENCRYPTION_MODE_AES_128_XTS,
 	BLK_ENCRYPTION_MODE_AES_256_XTS,
 	BLK_ENCRYPTION_MODE_AES_128_CBC_ESSIV,
 	BLK_ENCRYPTION_MODE_ADIANTUM,
 	BLK_ENCRYPTION_MODE_SM4_XTS,
+	BLK_ENCRYPTION_MODE_AES_128_CBC,
+	BLK_ENCRYPTION_MODE_AES_256_CBC,
 	BLK_ENCRYPTION_MODE_MAX,
 };
 
-- 
2.34.1

[PATCH 4/6] md: dm-crypt: Add additional algo modes for inline encryption

[Md Sadre Alam]

Add support for AES-XTS-128, AES-CBC-128 and AES-CBC-256 algo
modes for inline encryption.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/md/dm-crypt.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/md/dm-crypt.c b/drivers/md/dm-crypt.c
index c0257d961968..884cf76fc4c6 100644
--- a/drivers/md/dm-crypt.c
+++ b/drivers/md/dm-crypt.c
@@ -2482,8 +2482,14 @@ static int crypt_select_inline_crypt_mode(struct dm_target *ti, char *cipher,
 {
 	struct crypt_config *cc = ti->private;
 
-	if (strcmp(cipher, "xts(aes)") == 0) {
+	if (strcmp(cipher, "xts(aes128)") == 0) {
+		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_128_XTS;
+	} else if (strcmp(cipher, "xts(aes256)") == 0) {
 		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_256_XTS;
+	} else if (strcmp(cipher, "cbc(aes128)") == 0) {
+		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_128_CBC;
+	} else if (strcmp(cipher, "cbc(aes256)") == 0) {
+		cc->crypto_mode = BLK_ENCRYPTION_MODE_AES_256_CBC;
 	} else {
 		ti->error = "Invalid cipher for inline_crypt";
 		return -EINVAL;
-- 
2.34.1

[PATCH 5/6] mmc: cqhci: Add additional algo mode for inline encryption

[Md Sadre Alam]

Add support for AES-XTS-256, AES-CBC-128 and AES-CBC-256 in
cqhci_crypto_algs for inline encryption.

Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/mmc/host/cqhci-crypto.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/mmc/host/cqhci-crypto.c b/drivers/mmc/host/cqhci-crypto.c
index d5f4b6972f63..85ab7bb87886 100644
--- a/drivers/mmc/host/cqhci-crypto.c
+++ b/drivers/mmc/host/cqhci-crypto.c
@@ -16,10 +16,22 @@ static const struct cqhci_crypto_alg_entry {
 	enum cqhci_crypto_alg alg;
 	enum cqhci_crypto_key_size key_size;
 } cqhci_crypto_algs[BLK_ENCRYPTION_MODE_MAX] = {
+	[BLK_ENCRYPTION_MODE_AES_128_XTS] = {
+		.alg = CQHCI_CRYPTO_ALG_AES_XTS,
+		.key_size = CQHCI_CRYPTO_KEY_SIZE_128,
+	},
 	[BLK_ENCRYPTION_MODE_AES_256_XTS] = {
 		.alg = CQHCI_CRYPTO_ALG_AES_XTS,
 		.key_size = CQHCI_CRYPTO_KEY_SIZE_256,
 	},
+	[BLK_ENCRYPTION_MODE_AES_128_CBC] = {
+		.alg = CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC,
+		.key_size = CQHCI_CRYPTO_KEY_SIZE_128,
+	},
+	[BLK_ENCRYPTION_MODE_AES_256_CBC] = {
+		.alg = CQHCI_CRYPTO_ALG_BITLOCKER_AES_CBC,
+		.key_size = CQHCI_CRYPTO_KEY_SIZE_256,
+	},
 };
 
 static inline struct cqhci_host *
-- 
2.34.1

[PATCH 6/6] mmc: sdhci-msm: Add additional algo mode for inline encryption

[Md Sadre Alam]

Add support for AES-XTS-128, AES-CBC-128 and AES-CBS-256 modes for
inline encryption. Since ICE (Inline Crypto Engine) supports these
all modes

Co-developed-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
---
 drivers/mmc/host/sdhci-msm.c | 10 ++----
 drivers/soc/qcom/ice.c       | 65 +++++++++++++++++++++++++++++++-----
 2 files changed, 58 insertions(+), 17 deletions(-)

diff --git a/drivers/mmc/host/sdhci-msm.c b/drivers/mmc/host/sdhci-msm.c
index e113b99a3eab..fc1db58373ce 100644
--- a/drivers/mmc/host/sdhci-msm.c
+++ b/drivers/mmc/host/sdhci-msm.c
@@ -1867,17 +1867,11 @@ static int sdhci_msm_program_key(struct cqhci_host *cq_host,
 	struct sdhci_msm_host *msm_host = sdhci_pltfm_priv(pltfm_host);
 	union cqhci_crypto_cap_entry cap;
 
-	/* Only AES-256-XTS has been tested so far. */
 	cap = cq_host->crypto_cap_array[cfg->crypto_cap_idx];
-	if (cap.algorithm_id != CQHCI_CRYPTO_ALG_AES_XTS ||
-		cap.key_size != CQHCI_CRYPTO_KEY_SIZE_256)
-		return -EINVAL;
 
 	if (cfg->config_enable & CQHCI_CRYPTO_CONFIGURATION_ENABLE)
-		return qcom_ice_program_key(msm_host->ice,
-					    QCOM_ICE_CRYPTO_ALG_AES_XTS,
-					    QCOM_ICE_CRYPTO_KEY_SIZE_256,
-					    cfg->crypto_key,
+		return qcom_ice_program_key(msm_host->ice, cap.algorithm_id,
+					    cap.key_size, cfg->crypto_key,
 					    cfg->data_unit_size, slot);
 	else
 		return qcom_ice_evict_key(msm_host->ice, slot);
diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c
index fbab7fe5c652..f387b884c516 100644
--- a/drivers/soc/qcom/ice.c
+++ b/drivers/soc/qcom/ice.c
@@ -19,6 +19,9 @@
 
 #include <soc/qcom/ice.h>
 
+#define AES_128_CBC_KEY_SIZE			16
+#define AES_256_CBC_KEY_SIZE			32
+#define AES_128_XTS_KEY_SIZE			32
 #define AES_256_XTS_KEY_SIZE			64
 
 /* QCOM ICE registers */
@@ -161,36 +164,80 @@ int qcom_ice_suspend(struct qcom_ice *ice)
 }
 EXPORT_SYMBOL_GPL(qcom_ice_suspend);
 
+static int qcom_ice_get_algo_mode(struct qcom_ice *ice, u8 algorithm_id,
+				  u8 key_size, enum qcom_scm_ice_cipher *cipher,
+				  u32 *key_len)
+{
+	struct device *dev = ice->dev;
+
+	switch (key_size) {
+	case QCOM_ICE_CRYPTO_KEY_SIZE_128:
+		fallthrough;
+	case QCOM_ICE_CRYPTO_KEY_SIZE_256:
+		break;
+	default:
+		dev_err(dev, "Unhandled crypto key size %d\n", key_size);
+		return -EINVAL;
+	}
+
+	switch (algorithm_id) {
+	case QCOM_ICE_CRYPTO_ALG_AES_XTS:
+		if (key_size == QCOM_ICE_CRYPTO_KEY_SIZE_256) {
+			*cipher = QCOM_SCM_ICE_CIPHER_AES_256_XTS;
+			*key_len = AES_256_XTS_KEY_SIZE;
+		} else {
+			*cipher = QCOM_SCM_ICE_CIPHER_AES_128_XTS;
+			*key_len = AES_128_XTS_KEY_SIZE;
+		}
+		break;
+	case QCOM_ICE_CRYPTO_ALG_BITLOCKER_AES_CBC:
+		if (key_size == QCOM_ICE_CRYPTO_KEY_SIZE_256) {
+			*cipher = QCOM_SCM_ICE_CIPHER_AES_256_CBC;
+			*key_len = AES_256_CBC_KEY_SIZE;
+		} else {
+			*cipher = QCOM_SCM_ICE_CIPHER_AES_128_CBC;
+			*key_len = AES_128_CBC_KEY_SIZE;
+		}
+		break;
+	default:
+		dev_err_ratelimited(dev, "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
+				    algorithm_id, key_size);
+		return -EINVAL;
+	}
+
+	dev_info(dev, "cipher: %d key_size: %d", *cipher, *key_len);
+
+	return 0;
+}
+
 int qcom_ice_program_key(struct qcom_ice *ice,
 			 u8 algorithm_id, u8 key_size,
 			 const u8 crypto_key[], u8 data_unit_size,
 			 int slot)
 {
 	struct device *dev = ice->dev;
+	enum qcom_scm_ice_cipher cipher;
 	union {
 		u8 bytes[AES_256_XTS_KEY_SIZE];
 		u32 words[AES_256_XTS_KEY_SIZE / sizeof(u32)];
 	} key;
 	int i;
 	int err;
+	u32 key_len;
 
-	/* Only AES-256-XTS has been tested so far. */
-	if (algorithm_id != QCOM_ICE_CRYPTO_ALG_AES_XTS ||
-	    key_size != QCOM_ICE_CRYPTO_KEY_SIZE_256) {
-		dev_err_ratelimited(dev,
-				    "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
-				    algorithm_id, key_size);
+	if (qcom_ice_get_algo_mode(ice, algorithm_id, key_size, &cipher, &key_len)) {
+		dev_err(dev, "Unhandled crypto capability; algorithm_id=%d, key_size=%d\n",
+			algorithm_id, key_size);
 		return -EINVAL;
 	}
 
-	memcpy(key.bytes, crypto_key, AES_256_XTS_KEY_SIZE);
+	memcpy(key.bytes, crypto_key, key_len);
 
 	/* The SCM call requires that the key words are encoded in big endian */
 	for (i = 0; i < ARRAY_SIZE(key.words); i++)
 		__cpu_to_be32s(&key.words[i]);
 
-	err = qcom_scm_ice_set_key(slot, key.bytes, AES_256_XTS_KEY_SIZE,
-				   QCOM_SCM_ICE_CIPHER_AES_256_XTS,
+	err = qcom_scm_ice_set_key(slot, key.bytes, key_len, cipher,
 				   data_unit_size);
 
 	memzero_explicit(&key, sizeof(key));
-- 
2.34.1

Re: [PATCH 0/6] Add Additional algo mode for inline encryption

[Mikulas Patocka]

On Tue, 30 Jul 2024, Md Sadre Alam wrote:

> This series of patches add additional modes for inline encryption
> 
> This series of patches depends on [1] Add inline encryption support for dm-crypt
> 
> [1]: https://lore.kernel.org/all/b45d3b40-2587-04dc-9601-a9251dacf806@opensource.wdc.com/T/#ma01f08a941107217c93680fa25e96e8d406df790
> 
> These patches tested on IPQ9574 with eMMC ICE for raw partition
> encryption/decryption.

Hi

I discussed it with Milan Broz <gmazyland@gmail.com> and we concluded that 
there is no need to bloat dm-crypt with this logic.

We believe that you should create your own target (like 
"dm-inline-crypt"), it would work like a linear target and it will attach 
encryption requests to the bios that it processes.

Mikulas

Re: [PATCH 0/6] Add Additional algo mode for inline encryption

[Kamal Dasu]

[-- Attachment #1: Type: text/plain, Size: 985 bytes --]

This is not related to emulation, but was. upstream linux development

Kamal

On Wed, Jul 31, 2024 at 8:50 AM Mikulas Patocka <mpatocka@redhat.com> wrote:
>
>
>
> On Tue, 30 Jul 2024, Md Sadre Alam wrote:
>
> > This series of patches add additional modes for inline encryption
> >
> > This series of patches depends on [1] Add inline encryption support for dm-crypt
> >
> > [1]: https://lore.kernel.org/all/b45d3b40-2587-04dc-9601-a9251dacf806@opensource.wdc.com/T/#ma01f08a941107217c93680fa25e96e8d406df790
> >
> > These patches tested on IPQ9574 with eMMC ICE for raw partition
> > encryption/decryption.
>
> Hi
>
> I discussed it with Milan Broz <gmazyland@gmail.com> and we concluded that
> there is no need to bloat dm-crypt with this logic.
>
> We believe that you should create your own target (like
> "dm-inline-crypt"), it would work like a linear target and it will attach
> encryption requests to the bios that it processes.
>
> Mikulas
>
>

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Re: [PATCH 0/6] Add Additional algo mode for inline encryption

[Md Sadre Alam]

On 7/31/2024 6:18 PM, Mikulas Patocka wrote:
> 
> 
> On Tue, 30 Jul 2024, Md Sadre Alam wrote:
> 
>> This series of patches add additional modes for inline encryption
>>
>> This series of patches depends on [1] Add inline encryption support for dm-crypt
>>
>> [1]: https://lore.kernel.org/all/b45d3b40-2587-04dc-9601-a9251dacf806@opensource.wdc.com/T/#ma01f08a941107217c93680fa25e96e8d406df790
>>
>> These patches tested on IPQ9574 with eMMC ICE for raw partition
>> encryption/decryption.
> 
> Hi
> 
> I discussed it with Milan Broz <gmazyland@gmail.com> and we concluded that
> there is no need to bloat dm-crypt with this logic.
> 
> We believe that you should create your own target (like
> "dm-inline-crypt"), it would work like a linear target and it will attach
> encryption requests to the bios that it processes.
> 
   Thanks for reviewing. Will create new target driver "dm-inline-crypt".

> Mikulas
>