* [PATCH] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
@ 2021-03-19 17:39 Tony Luck
2021-03-20 11:22 ` [tip: x86/cpu] " tip-bot2 for Tony Luck
0 siblings, 1 reply; 2+ messages in thread
From: Tony Luck @ 2021-03-19 17:39 UTC (permalink / raw)
To: Borislav Petkov; +Cc: x86, linux-kernel, Tony Luck
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index e309476743b7..acfd5d9f93c6 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
--
2.29.2
^ permalink raw reply [flat|nested] 2+ messages in thread
* [tip: x86/cpu] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
2021-03-19 17:39 [PATCH] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN Tony Luck
@ 2021-03-20 11:22 ` tip-bot2 for Tony Luck
0 siblings, 0 replies; 2+ messages in thread
From: tip-bot2 for Tony Luck @ 2021-03-20 11:22 UTC (permalink / raw)
To: linux-tip-commits; +Cc: Tony Luck, Ingo Molnar, x86, linux-kernel
The following commit has been merged into the x86/cpu branch of tip:
Commit-ID: a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab
Gitweb: https://git.kernel.org/tip/a331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab
Author: Tony Luck <tony.luck@intel.com>
AuthorDate: Fri, 19 Mar 2021 10:39:19 -07:00
Committer: Ingo Molnar <mingo@kernel.org>
CommitterDate: Sat, 20 Mar 2021 12:12:10 +01:00
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
New CPU model, same MSRs to control and read the inventory number.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
---
arch/x86/kernel/cpu/mce/intel.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c
index e309476..acfd5d9 100644
--- a/arch/x86/kernel/cpu/mce/intel.c
+++ b/arch/x86/kernel/cpu/mce/intel.c
@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
+ case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM:
^ permalink raw reply [flat|nested] 2+ messages in thread
end of thread, other threads:[~2021-03-20 11:23 UTC | newest]
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2021-03-19 17:39 [PATCH] x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN Tony Luck
2021-03-20 11:22 ` [tip: x86/cpu] " tip-bot2 for Tony Luck
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