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From: Rob Herring <robh@kernel.org>
To: niravkumar.l.rabara@intel.com
Cc: linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
	Andrew Lunn <andrew@lunn.ch>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com>,
	Richard Cochran <richardcochran@gmail.com>,
	Wen Ping <wen.ping.teh@intel.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	devicetree@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
	Dinh Nguyen <dinguyen@kernel.org>,
	netdev@vger.kernel.org, Philipp Zabel <p.zabel@pengutronix.de>
Subject: Re: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets
Date: Sun, 18 Jun 2023 20:15:27 -0600	[thread overview]
Message-ID: <168714092772.2813.6608190334028827343.robh@kernel.org> (raw)
In-Reply-To: <20230618132235.728641-3-niravkumar.l.rabara@intel.com>


On Sun, 18 Jun 2023 21:22:33 +0800, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Add clock and reset ID definitions for Intel Agilex5 SoCFPGA
> 
> Co-developed-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  .../bindings/clock/intel,agilex5.yaml         |  42 ++++++++
>  include/dt-bindings/clock/agilex5-clock.h     | 100 ++++++++++++++++++
>  .../dt-bindings/reset/altr,rst-mgr-agilex5.h  |  79 ++++++++++++++
>  3 files changed, 221 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml
>  create mode 100644 include/dt-bindings/clock/agilex5-clock.h
>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/clock/intel,agilex5.yaml: title: 'Intel SoCFPGA Agilex5 platform clock controller binding' should not be valid under {'pattern': '([Bb]inding| [Ss]chema)'}
	hint: Everything is a binding/schema, no need to say it. Describe what hardware the binding is for.
	from schema $id: http://devicetree.org/meta-schemas/core.yaml#

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230618132235.728641-3-niravkumar.l.rabara@intel.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.


  parent reply	other threads:[~2023-06-19  2:15 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-18 13:22 [PATCH 0/4] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-06-18 18:47   ` Krzysztof Kozlowski
2023-06-20 14:12     ` niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets niravkumar.l.rabara
2023-06-18 18:49   ` Krzysztof Kozlowski
2023-06-20 10:39     ` wen.ping.teh
2023-06-20 11:06       ` Krzysztof Kozlowski
2023-06-21 10:45         ` wen.ping.teh
2023-06-19  2:15   ` Rob Herring [this message]
2023-06-18 13:22 ` [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform niravkumar.l.rabara
2023-06-20 14:42   ` Dinh Nguyen
2023-06-18 13:22 ` [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA niravkumar.l.rabara
2023-06-18 18:56   ` Krzysztof Kozlowski
2023-06-20 14:07     ` niravkumar.l.rabara
2023-08-01  1:02 ` [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-08-01  1:02   ` [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-08-01 20:53     ` Conor Dooley
2023-08-01  1:02   ` [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 niravkumar.l.rabara
2023-08-01 20:55     ` Conor Dooley
2023-08-01  1:02   ` [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager niravkumar.l.rabara
2023-08-01 20:57     ` Conor Dooley
2023-08-02  3:06       ` Rabara, Niravkumar L
2023-08-02  6:58         ` Conor Dooley
2023-08-02  2:58     ` [PATCH v3 " niravkumar.l.rabara
2023-08-02  7:02       ` Conor Dooley
2023-08-02  7:14         ` Rabara, Niravkumar L
2023-08-06 17:53           ` Dinh Nguyen
2023-08-06 19:35     ` [PATCH v2 " Krzysztof Kozlowski
2023-08-07  3:56       ` Rabara, Niravkumar L
2023-08-01  1:02   ` [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 niravkumar.l.rabara
2023-08-08 11:03     ` Dinh Nguyen
2023-08-09 21:28       ` Stephen Boyd
2023-08-10 10:56         ` Dinh Nguyen
2023-08-09 21:26     ` Stephen Boyd
2023-08-13 12:53       ` Rabara, Niravkumar L
2023-08-14  2:48         ` Dinh Nguyen
2023-08-14  2:59           ` Rabara, Niravkumar L
2023-08-01  1:02   ` [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA niravkumar.l.rabara

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