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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: niravkumar.l.rabara@intel.com, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>, Andrew Lunn <andrew@lunn.ch>,
	Dinh Nguyen <dinguyen@kernel.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Philipp Zabel <p.zabel@pengutronix.de>,
	Wen Ping <wen.ping.teh@intel.com>,
	Richard Cochran <richardcochran@gmail.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-clk@vger.kernel.org, netdev@vger.kernel.org,
	Adrian Ng Ho Yin <adrian.ho.yin.ng@intel.com>
Subject: Re: [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets
Date: Sun, 18 Jun 2023 20:49:52 +0200	[thread overview]
Message-ID: <8d5f38e6-2ca6-2c61-da29-1d4d2a3df569@linaro.org> (raw)
In-Reply-To: <20230618132235.728641-3-niravkumar.l.rabara@intel.com>

On 18/06/2023 15:22, niravkumar.l.rabara@intel.com wrote:
> From: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> 
> Add clock and reset ID definitions for Intel Agilex5 SoCFPGA
> 
> Co-developed-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
> Signed-off-by: Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> ---
>  .../bindings/clock/intel,agilex5.yaml         |  42 ++++++++
>  include/dt-bindings/clock/agilex5-clock.h     | 100 ++++++++++++++++++
>  .../dt-bindings/reset/altr,rst-mgr-agilex5.h  |  79 ++++++++++++++
>  3 files changed, 221 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/intel,agilex5.yaml
>  create mode 100644 include/dt-bindings/clock/agilex5-clock.h
>  create mode 100644 include/dt-bindings/reset/altr,rst-mgr-agilex5.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/intel,agilex5.yaml b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml
> new file mode 100644
> index 000000000000..e408c52deefa
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/intel,agilex5.yaml

Filename matching compatible, so missing "clk"

> @@ -0,0 +1,42 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/intel,agilex5.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Intel SoCFPGA Agilex5 platform clock controller binding

Drop "binding"

> +
> +maintainers:
> +  - Teh Wen Ping <wen.ping.teh@intel.com>
> +  - Niravkumar L Rabara <niravkumar.l.rabara@intel.com>
> +
> +description:
> +  The Intel Agilex5 Clock controller is an integrated clock controller, which
> +  generates and supplies to all modules.

"generates and supplies" what?

> +
> +properties:
> +  compatible:
> +    const: intel,agilex5-clkmgr


Why "clkmgr", not "clk"? You did not call it Clock manager anywhere in
the description or title.

> +
> +  '#clock-cells':
> +    const: 1
> +
> +  reg:
> +    maxItems: 1
> +
> +required:
> +  - compatible
> +  - reg
> +  - '#clock-cells'

Keep the same order as in properties:

> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock controller node:
> +  - |
> +    clkmgr: clock-controller@10d10000 {
> +      compatible = "intel,agilex5-clkmgr";
> +      reg = <0x10d10000 0x1000>;
> +      #clock-cells = <1>;
> +    };
> +...
> diff --git a/include/dt-bindings/clock/agilex5-clock.h b/include/dt-bindings/clock/agilex5-clock.h
> new file mode 100644
> index 000000000000..4505b352cd83
> --- /dev/null
> +++ b/include/dt-bindings/clock/agilex5-clock.h

Filename the same as binding. Missing vendor prefix, entirely different
device name.

> @@ -0,0 +1,100 @@
> +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
> +/*
> + * Copyright (C) 2022, Intel Corporation
> + */

...

> +
> +#endif	/* __AGILEX5_CLOCK_H */
> diff --git a/include/dt-bindings/reset/altr,rst-mgr-agilex5.h b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h
> new file mode 100644
> index 000000000000..81e5e8c89893
> --- /dev/null
> +++ b/include/dt-bindings/reset/altr,rst-mgr-agilex5.h

Same filename as binding.

But why do you need this file? Your device is not a reset controller.

Best regards,
Krzysztof


  reply	other threads:[~2023-06-18 18:50 UTC|newest]

Thread overview: 39+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-06-18 13:22 [PATCH 0/4] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 1/4] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-06-18 18:47   ` Krzysztof Kozlowski
2023-06-20 14:12     ` niravkumar.l.rabara
2023-06-18 13:22 ` [PATCH 2/4] dt-bindings: clock: Add Intel Agilex5 clocks and resets niravkumar.l.rabara
2023-06-18 18:49   ` Krzysztof Kozlowski [this message]
2023-06-20 10:39     ` wen.ping.teh
2023-06-20 11:06       ` Krzysztof Kozlowski
2023-06-21 10:45         ` wen.ping.teh
2023-06-19  2:15   ` Rob Herring
2023-06-18 13:22 ` [PATCH 3/4] clk: socfpga: agilex5: Add clock driver for Agilex5 platform niravkumar.l.rabara
2023-06-20 14:42   ` Dinh Nguyen
2023-06-18 13:22 ` [PATCH 4/4] arm64: dts: agilex5: Add initial support for Intel's Agilex5 SoCFPGA niravkumar.l.rabara
2023-06-18 18:56   ` Krzysztof Kozlowski
2023-06-20 14:07     ` niravkumar.l.rabara
2023-08-01  1:02 ` [PATCH v2 0/5] Add support for Agilex5 SoCFPGA platform niravkumar.l.rabara
2023-08-01  1:02   ` [PATCH v2 1/5] dt-bindings: intel: Add Intel Agilex5 compatible niravkumar.l.rabara
2023-08-01 20:53     ` Conor Dooley
2023-08-01  1:02   ` [PATCH v2 2/5] dt-bindings: reset: add reset IDs for Agilex5 niravkumar.l.rabara
2023-08-01 20:55     ` Conor Dooley
2023-08-01  1:02   ` [PATCH v2 3/5] dt-bindings: clock: add Intel Agilex5 clock manager niravkumar.l.rabara
2023-08-01 20:57     ` Conor Dooley
2023-08-02  3:06       ` Rabara, Niravkumar L
2023-08-02  6:58         ` Conor Dooley
2023-08-02  2:58     ` [PATCH v3 " niravkumar.l.rabara
2023-08-02  7:02       ` Conor Dooley
2023-08-02  7:14         ` Rabara, Niravkumar L
2023-08-06 17:53           ` Dinh Nguyen
2023-08-06 19:35     ` [PATCH v2 " Krzysztof Kozlowski
2023-08-07  3:56       ` Rabara, Niravkumar L
2023-08-01  1:02   ` [PATCH v2 4/5] clk: socfpga: agilex: add clock driver for the Agilex5 niravkumar.l.rabara
2023-08-08 11:03     ` Dinh Nguyen
2023-08-09 21:28       ` Stephen Boyd
2023-08-10 10:56         ` Dinh Nguyen
2023-08-09 21:26     ` Stephen Boyd
2023-08-13 12:53       ` Rabara, Niravkumar L
2023-08-14  2:48         ` Dinh Nguyen
2023-08-14  2:59           ` Rabara, Niravkumar L
2023-08-01  1:02   ` [PATCH v2 5/5] arm64: dts: agilex5: add initial support for Intel Agilex5 SoCFPGA niravkumar.l.rabara

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