mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
* [patch 0/5] x86/microcode/amd: Use cached microcode for early loading
@ 2023-10-10 15:08 Thomas Gleixner
  2023-10-10 15:08 ` [patch 1/5] x86/microcode/amd: Use correct per CPU ucode_cpu_info Thomas Gleixner
                   ` (4 more replies)
  0 siblings, 5 replies; 17+ messages in thread
From: Thomas Gleixner @ 2023-10-10 15:08 UTC (permalink / raw)
  To: LKML; +Cc: x86, Borislav Petkov

When Borislav applied the microcode overhaul series:

     https://lore.kernel.org/all/20231002115506.217091296@linutronix.de/

he partially reverted patch 15:

     https://lore.kernel.org/all/20231006132617.GOZSAK+YCEwVsEuUdr@fat_crate.local/

to keep AMD suspend/resume working.

After looking at this in detail it turned out that AMD does not use the
microcode cache for the early loading during AP bringup and tries to find
the microcode in builtin/initrd.

That in turn requires to have a CPU hotplug callback for late hotplug which
ensures that the microcode is updated. That's actually too late as CPUID
bits are evaluated already before that callback is invoked.

The reason why this was done is the horrible 32bit hack which invoked the
early loader before paging is enabled.

That's gone now which in turn allows to remove all this by initializing the
microcode cache before the APs are brought up and use the microcode cache
for early loading on APs during boot, manual hotplug and resume.

This gets finally rid of the hotplug callback and the ugly initrd_gone
hackery which was required to make the post init AP loader work.

The series applies on top of:

 git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/microcode

Thanks,

	tglx
---
 amd.c      |   34 +++++++++++++++++++++-------------
 core.c     |   44 +++-----------------------------------------
 internal.h |    4 ----
 3 files changed, 24 insertions(+), 58 deletions(-)


^ permalink raw reply	[flat|nested] 17+ messages in thread
* [patch V5 23/39] x86/microcode/amd: Use cached microcode for AP load
@ 2023-10-17 21:23 Thomas Gleixner
  2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
  2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner
  0 siblings, 2 replies; 17+ messages in thread
From: Thomas Gleixner @ 2023-10-17 21:23 UTC (permalink / raw)
  To: LKML; +Cc: x86, Borislav Petkov

From: Thomas Gleixner <tglx@linutronix.de>

Now that the microcode cache is initialized before the APs are brought up,
there is no point in scanning builtin/initrd microcode during AP
loading.

Convert the AP loader to utilize the cache, which in turn makes the CPU
hotplug callback which applies the microcode after initrd/builtin is gone
obsolete as the early loading during late hotplug operations including the
resume path depends now only on the cache.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
---
 arch/x86/kernel/cpu/microcode/amd.c      |   20 +++++++++++---------
 arch/x86/kernel/cpu/microcode/core.c     |   15 ++-------------
 arch/x86/kernel/cpu/microcode/internal.h |    2 --
 3 files changed, 13 insertions(+), 24 deletions(-)
---
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -496,7 +496,7 @@ static bool get_builtin_microcode(struct
 	return false;
 }
 
-static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret)
+static void __init find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret)
 {
 	struct cpio_data cp;
 
@@ -506,12 +506,12 @@ static void find_blobs_in_containers(uns
 	*ret = cp;
 }
 
-static void apply_ucode_from_containers(unsigned int cpuid_1_eax)
+void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax)
 {
 	struct cpio_data cp = { };
 
 	/* Needed in load_microcode_amd() */
-	ucode_cpu_info[smp_processor_id()].cpu_sig.sig = cpuid_1_eax;
+	ucode_cpu_info[0].cpu_sig.sig = cpuid_1_eax;
 
 	find_blobs_in_containers(cpuid_1_eax, &cp);
 	if (!(cp.data && cp.size))
@@ -520,11 +520,6 @@ static void apply_ucode_from_containers(
 	early_apply_microcode(cpuid_1_eax, cp.data, cp.size);
 }
 
-void load_ucode_amd_early(unsigned int cpuid_1_eax)
-{
-	return apply_ucode_from_containers(cpuid_1_eax);
-}
-
 static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size);
 
 static int __init save_microcode_in_initrd(void)
@@ -608,7 +603,6 @@ static struct ucode_patch *find_patch(un
 	struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
 	u16 equiv_id;
 
-
 	equiv_id = find_equiv_id(&equiv_table, uci->cpu_sig.sig);
 	if (!equiv_id)
 		return NULL;
@@ -710,6 +704,14 @@ static enum ucode_state apply_microcode_
 	return ret;
 }
 
+void load_ucode_amd_ap(unsigned int cpuid_1_eax)
+{
+	unsigned int cpu = smp_processor_id();
+
+	ucode_cpu_info[cpu].cpu_sig.sig = cpuid_1_eax;
+	apply_microcode_amd(cpu);
+}
+
 static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
 {
 	u32 equiv_tbl_len;
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -154,7 +154,7 @@ void __init load_ucode_bsp(void)
 	if (intel)
 		load_ucode_intel_bsp();
 	else
-		load_ucode_amd_early(cpuid_1_eax);
+		load_ucode_amd_bsp(cpuid_1_eax);
 }
 
 void load_ucode_ap(void)
@@ -173,7 +173,7 @@ void load_ucode_ap(void)
 		break;
 	case X86_VENDOR_AMD:
 		if (x86_family(cpuid_1_eax) >= 0x10)
-			load_ucode_amd_early(cpuid_1_eax);
+			load_ucode_amd_ap(cpuid_1_eax);
 		break;
 	default:
 		break;
@@ -494,15 +494,6 @@ static struct syscore_ops mc_syscore_ops
 	.resume	= microcode_bsp_resume,
 };
 
-static int mc_cpu_starting(unsigned int cpu)
-{
-	enum ucode_state err = microcode_ops->apply_microcode(cpu);
-
-	pr_debug("%s: CPU%d, err: %d\n", __func__, cpu, err);
-
-	return err == UCODE_ERROR;
-}
-
 static int mc_cpu_online(unsigned int cpu)
 {
 	struct device *dev = get_cpu_device(cpu);
@@ -590,8 +581,6 @@ static int __init microcode_init(void)
 	schedule_on_each_cpu(setup_online_cpu);
 
 	register_syscore_ops(&mc_syscore_ops);
-	cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting",
-				  mc_cpu_starting, NULL);
 	cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online",
 				  mc_cpu_online, mc_cpu_down_prep);
 
--- a/arch/x86/kernel/cpu/microcode/internal.h
+++ b/arch/x86/kernel/cpu/microcode/internal.h
@@ -91,7 +91,6 @@ extern bool initrd_gone;
 #ifdef CONFIG_CPU_SUP_AMD
 void load_ucode_amd_bsp(unsigned int family);
 void load_ucode_amd_ap(unsigned int family);
-void load_ucode_amd_early(unsigned int cpuid_1_eax);
 int save_microcode_in_initrd_amd(unsigned int family);
 void reload_ucode_amd(unsigned int cpu);
 struct microcode_ops *init_amd_microcode(void);
@@ -99,7 +98,6 @@ void exit_amd_microcode(void);
 #else /* CONFIG_CPU_SUP_AMD */
 static inline void load_ucode_amd_bsp(unsigned int family) { }
 static inline void load_ucode_amd_ap(unsigned int family) { }
-static inline void load_ucode_amd_early(unsigned int family) { }
 static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; }
 static inline void reload_ucode_amd(unsigned int cpu) { }
 static inline struct microcode_ops *init_amd_microcode(void) { return NULL; }


^ permalink raw reply	[flat|nested] 17+ messages in thread

end of thread, other threads:[~2023-10-24 13:22 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-10 15:08 [patch 0/5] x86/microcode/amd: Use cached microcode for early loading Thomas Gleixner
2023-10-10 15:08 ` [patch 1/5] x86/microcode/amd: Use correct per CPU ucode_cpu_info Thomas Gleixner
2023-10-11  9:01   ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-20 11:37   ` tip-bot2 for Thomas Gleixner
2023-10-24 13:21   ` tip-bot2 for Thomas Gleixner
2023-10-10 15:08 ` [patch 2/5] x86/microcode/amd: Cache builtin microcode too Thomas Gleixner
2023-10-11  9:01   ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-20 11:37   ` tip-bot2 for Thomas Gleixner
2023-10-24 13:21   ` tip-bot2 for Thomas Gleixner
2023-10-10 15:08 ` [patch 3/5] x86/microcode/amd: Cache builtin/initrd microcode early Thomas Gleixner
2023-10-11  9:01   ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-10 15:08 ` [patch 4/5] x86/microcode/amd: Use cached microcode for AP load Thomas Gleixner
2023-10-11  9:01   ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-10 15:08 ` [patch 5/5] x86/microcode: Mop up early loading leftovers Thomas Gleixner
2023-10-11  9:00   ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-17 21:23 [patch V5 23/39] x86/microcode/amd: Use cached microcode for AP load Thomas Gleixner
2023-10-20 11:37 ` [tip: x86/microcode] " tip-bot2 for Thomas Gleixner
2023-10-24 13:21 ` tip-bot2 for Thomas Gleixner

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®