[PATCH 0/2] drm/imagination: Miscellaneous improvements and utility functions

[PATCH 0/2] drm/imagination: Miscellaneous improvements and utility functions

[Alexandru Dadu]

Code cleanup - wrong soft reset code removed from startup.
Utiity function - added function to write and read back registers.

Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
Alessio Belle (2):
      drm/imagination: Remove wrong soft reset code from GPU start sequence
      drm/imagination: Add utility function to write and read back register

 drivers/gpu/drm/imagination/pvr_device.h       | 28 +++++++++++++++++++
 drivers/gpu/drm/imagination/pvr_fw_meta.c      |  5 ++--
 drivers/gpu/drm/imagination/pvr_fw_startstop.c | 37 +++++++-------------------
 3 files changed, 39 insertions(+), 31 deletions(-)
---
base-commit: 6e375de99d0c420169481fcd36064177ab55b09d
change-id: 20261006-b4-utility-function-to-rw-regs-0777c17380b9

Best regards,
--  
Alexandru Dadu <alexandru.dadu@imgtec.com>

[PATCH 1/2] drm/imagination: Remove wrong soft reset code from GPU start sequence

[Alexandru Dadu]

From: Alessio Belle <alessio.belle@imgtec.com>

SOFT_RESET2 is not dependent on XE_TPU2, but on S7_TOP_INFRASTRUCTURE.

Since no released Rogue cores have that feature or register, remove any
writes to it.

Fixes: cc1aeedb98ad ("drm/imagination: Implement firmware infrastructure and META FW support")
Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
 drivers/gpu/drm/imagination/pvr_fw_startstop.c | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 98ca2692239d..34c757267a22 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -110,10 +110,12 @@ rogue_slc_init(struct pvr_device *pvr_dev)
 int
 pvr_fw_start(struct pvr_device *pvr_dev)
 {
-	bool has_reset2 = PVR_HAS_FEATURE(pvr_dev, xe_tpu2);
 	u64 soft_reset_mask;
 	int err;
 
+	/* No Rogue cores should have this feature which requires additional reset steps. */
+	WARN_ON_ONCE(PVR_HAS_FEATURE(pvr_dev, s7_top_infrastructure));
+
 	if (PVR_HAS_FEATURE(pvr_dev, pbe2_in_xe))
 		soft_reset_mask = ROGUE_CR_SOFT_RESET__PBE2_XE__MASKFULL;
 	else
@@ -133,32 +135,20 @@ pvr_fw_start(struct pvr_device *pvr_dev)
 
 	/* Set Rogue in soft-reset. */
 	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask);
-	if (has_reset2)
-		pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, ROGUE_CR_SOFT_RESET2_MASKFULL);
 
 	/* Read soft-reset to fence previous write in order to clear the SOCIF pipeline. */
 	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
-	if (has_reset2)
-		(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2);
 
 	/* Take Rascal and Dust out of reset. */
 	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET,
 		       soft_reset_mask ^ ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN);
-	if (has_reset2)
-		pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, 0);
 
 	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
-	if (has_reset2)
-		(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2);
 
 	/* Take everything out of reset but the FW processor. */
 	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, ROGUE_CR_SOFT_RESET_GARTEN_EN);
-	if (has_reset2)
-		pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET2, 0);
 
 	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
-	if (has_reset2)
-		(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET2);
 
 	err = rogue_slc_init(pvr_dev);
 	if (err)

-- 
2.43.0

[PATCH 2/2] drm/imagination: Add utility function to write and read back register

[Alexandru Dadu]

From: Alessio Belle <alessio.belle@imgtec.com>

Used to avoid repeating the same pattern multiple times.

Signed-off-by: Alessio Belle <alessio.belle@imgtec.com>
Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
---
 drivers/gpu/drm/imagination/pvr_device.h       | 28 ++++++++++++++++++++++++++
 drivers/gpu/drm/imagination/pvr_fw_meta.c      |  5 ++---
 drivers/gpu/drm/imagination/pvr_fw_startstop.c | 21 ++++++-------------
 3 files changed, 36 insertions(+), 18 deletions(-)

diff --git a/drivers/gpu/drm/imagination/pvr_device.h b/drivers/gpu/drm/imagination/pvr_device.h
index d51c57cf9332..c246122b4caf 100644
--- a/drivers/gpu/drm/imagination/pvr_device.h
+++ b/drivers/gpu/drm/imagination/pvr_device.h
@@ -606,6 +606,34 @@ pvr_cr_write64(struct pvr_device *pvr_dev, u32 reg, u64 val)
 	iowrite64(val, pvr_dev->regs + reg);
 }
 
+/**
+ * pvr_cr_write_fenced32() - Write to a 32-bit register in a PowerVR device and fence the write
+ * @pvr_dev: Target PowerVR device.
+ * @reg: Target register.
+ * @val: Value to write.
+ */
+static __always_inline void
+pvr_cr_write_fenced32(struct pvr_device *pvr_dev, u32 reg, u32 val)
+{
+	pvr_cr_write32(pvr_dev, reg, val);
+	/* Read back register to fence previous write in order to clear the SOCIF pipeline */
+	(void)pvr_cr_read32(pvr_dev, reg);
+}
+
+/**
+ * pvr_cr_write_fenced64() - Write to a 64-bit register in a PowerVR device and fence the write
+ * @pvr_dev: Target PowerVR device.
+ * @reg: Target register.
+ * @val: Value to write.
+ */
+static __always_inline void
+pvr_cr_write_fenced64(struct pvr_device *pvr_dev, u32 reg, u64 val)
+{
+	pvr_cr_write64(pvr_dev, reg, val);
+	/* Read back register to fence previous write in order to clear the SOCIF pipeline */
+	(void)pvr_cr_read64(pvr_dev, reg);
+}
+
 /**
  * pvr_cr_poll_reg32() - Wait for a 32-bit register to match a given value by
  *                       polling
diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/imagination/pvr_fw_meta.c
index 84f568b5510f..38a91dcb66cb 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_meta.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c
@@ -48,9 +48,8 @@ pvr_meta_cr_read32(struct pvr_device *pvr_dev, u32 reg_addr, u32 *reg_value_out)
 		return err;
 
 	/* Issue a Read. */
-	pvr_cr_write32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0,
-		       reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN);
-	(void)pvr_cr_read32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0); /* Fence write. */
+	pvr_cr_write_fenced32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL0,
+			      reg_addr | ROGUE_CR_META_SP_MSLVCTRL0_RD_EN);
 
 	/* Wait for Slave Port to be Ready. */
 	err = pvr_cr_poll_reg32(pvr_dev, ROGUE_CR_META_SP_MSLVCTRL1,
diff --git a/drivers/gpu/drm/imagination/pvr_fw_startstop.c b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
index 34c757267a22..7db7f16e62fd 100644
--- a/drivers/gpu/drm/imagination/pvr_fw_startstop.c
+++ b/drivers/gpu/drm/imagination/pvr_fw_startstop.c
@@ -126,29 +126,21 @@ pvr_fw_start(struct pvr_device *pvr_dev)
 		 * Disable the default sys_bus_secure protection to perform
 		 * minimal setup.
 		 */
-		pvr_cr_write32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE, 0);
-		(void)pvr_cr_read32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE); /* Fence write */
+		pvr_cr_write_fenced32(pvr_dev, ROGUE_CR_SYS_BUS_SECURE, 0);
 	}
 
 	if (pvr_dev->fw_dev.processor_type == PVR_FW_PROCESSOR_TYPE_RISCV)
 		pvr_cr_write32(pvr_dev, ROGUE_CR_FWCORE_BOOT, 0);
 
 	/* Set Rogue in soft-reset. */
-	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask);
-
-	/* Read soft-reset to fence previous write in order to clear the SOCIF pipeline. */
-	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
+	pvr_cr_write_fenced64(pvr_dev, ROGUE_CR_SOFT_RESET, soft_reset_mask);
 
 	/* Take Rascal and Dust out of reset. */
-	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET,
-		       soft_reset_mask ^ ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN);
-
-	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
+	pvr_cr_write_fenced64(pvr_dev, ROGUE_CR_SOFT_RESET,
+			      soft_reset_mask ^ ROGUE_CR_SOFT_RESET_RASCALDUSTS_EN);
 
 	/* Take everything out of reset but the FW processor. */
-	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, ROGUE_CR_SOFT_RESET_GARTEN_EN);
-
-	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
+	pvr_cr_write_fenced64(pvr_dev, ROGUE_CR_SOFT_RESET, ROGUE_CR_SOFT_RESET_GARTEN_EN);
 
 	err = rogue_slc_init(pvr_dev);
 	if (err)
@@ -168,8 +160,7 @@ pvr_fw_start(struct pvr_device *pvr_dev)
 	/* Need to wait for at least 16 cycles before taking the FW processor out of reset ... */
 	udelay(3);
 
-	pvr_cr_write64(pvr_dev, ROGUE_CR_SOFT_RESET, 0x0);
-	(void)pvr_cr_read64(pvr_dev, ROGUE_CR_SOFT_RESET);
+	pvr_cr_write_fenced64(pvr_dev, ROGUE_CR_SOFT_RESET, 0x0);
 
 	/* ... and afterwards. */
 	udelay(3);

-- 
2.43.0

Re: [PATCH 0/2] drm/imagination: Miscellaneous improvements and utility functions

[Brajesh Gupta]

On Tue, 2026-10-06 at 14:06 +0300, Alexandru Dadu wrote:
Hi Dadu,
> Code cleanup - wrong soft reset code removed from startup.
> Utiity function - added function to write and read back registers.
> 
> Signed-off-by: Alexandru Dadu <alexandru.dadu@imgtec.com>
> ---
> Alessio Belle (2):
>       drm/imagination: Remove wrong soft reset code from GPU start sequence
>       drm/imagination: Add utility function to write and read back register
> 
>  drivers/gpu/drm/imagination/pvr_device.h       | 28 +++++++++++++++++++
>  drivers/gpu/drm/imagination/pvr_fw_meta.c      |  5 ++--
>  drivers/gpu/drm/imagination/pvr_fw_startstop.c | 37 +++++++-------------------
>  3 files changed, 39 insertions(+), 31 deletions(-)
> ---
For the whole series:
Reviewed-by: Brajesh Gupta <brajesh.gupta@imgtec.com>

Thanks,
Brajesh
> base-commit: 6e375de99d0c420169481fcd36064177ab55b09d
> change-id: 20261006-b4-utility-function-to-rw-regs-0777c17380b9
> 
> Best regards,
> --  
> Alexandru Dadu <alexandru.dadu@imgtec.com>
>