[PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro

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* [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro
@ 2024-05-10 17:58 srinivas.kandagatla
  2024-05-10 17:58 ` [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version srinivas.kandagatla
                   ` (2 more replies)
  0 siblings, 3 replies; 6+ messages in thread
From: srinivas.kandagatla @ 2024-05-10 17:58 UTC (permalink / raw)
  To: broonie
  Cc: perex, tiwai, alsa-devel, lgirdwood, linux-kernel,
	krzysztof.kozlowski, neil.armstrong, Srinivas Kandagatla

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

This patchset adds support to reading codec version and also adds
support for v2.6 codec version in rx macro. 

LPASS 2.6 has changes in some of the rx block which are required to get
headset functional correctly.

Tested this on X13s and x1e80100 crd.

Thanks,
Srini

Srinivas Kandagatla (2):
  ASoC: codecs: lpass-macro: add helpers to get codec version
  ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version

 sound/soc/codecs/lpass-macro-common.c |  14 +
 sound/soc/codecs/lpass-macro-common.h |  35 ++
 sound/soc/codecs/lpass-rx-macro.c     | 565 +++++++++++++++++++-------
 sound/soc/codecs/lpass-va-macro.c     |  29 ++
 4 files changed, 488 insertions(+), 155 deletions(-)

-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version
  2024-05-10 17:58 [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro srinivas.kandagatla
@ 2024-05-10 17:58 ` srinivas.kandagatla
  2024-05-15 14:28   ` Dan Carpenter
  2024-05-10 17:58 ` [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 " srinivas.kandagatla
  2024-06-17 17:26 ` [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro Mark Brown
  2 siblings, 1 reply; 6+ messages in thread
From: srinivas.kandagatla @ 2024-05-10 17:58 UTC (permalink / raw)
  To: broonie
  Cc: perex, tiwai, alsa-devel, lgirdwood, linux-kernel,
	krzysztof.kozlowski, neil.armstrong, Srinivas Kandagatla

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

LPASS Digital codec have changes in register layout across multiple
versions. Add a proper way read the codec version allowint all the lpass
macro drivers (tx, rx, wsa, va) to configure the registers correctly.

LPASS VA macro has the required registers to read the codec version.
Read the the version and make it available to other lpass codec macros
using the common helper functions.

Existing method of using LPASS IP version is not accurate as the same
the codec versioning is totally independent of LPASS IP block versions.

These helper functions should be able to provide a convient way to get
the codec version, and will help scale the drivers in right direction.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 sound/soc/codecs/lpass-macro-common.c | 14 +++++++++++
 sound/soc/codecs/lpass-macro-common.h | 35 +++++++++++++++++++++++++++
 sound/soc/codecs/lpass-va-macro.c     | 29 ++++++++++++++++++++++
 3 files changed, 78 insertions(+)

diff --git a/sound/soc/codecs/lpass-macro-common.c b/sound/soc/codecs/lpass-macro-common.c
index da1b422250b8..a640bf88a6cd 100644
--- a/sound/soc/codecs/lpass-macro-common.c
+++ b/sound/soc/codecs/lpass-macro-common.c
@@ -11,6 +11,8 @@
 
 #include "lpass-macro-common.h"
 
+static int lpass_codec_version;
+
 struct lpass_macro *lpass_macro_pds_init(struct device *dev)
 {
 	struct lpass_macro *l_pds;
@@ -66,5 +68,17 @@ void lpass_macro_pds_exit(struct lpass_macro *pds)
 }
 EXPORT_SYMBOL_GPL(lpass_macro_pds_exit);
 
+void lpass_macro_set_codec_version(int version)
+{
+	lpass_codec_version = version;
+}
+EXPORT_SYMBOL_GPL(lpass_macro_set_codec_version);
+
+int lpass_macro_get_codec_version(void)
+{
+	return lpass_codec_version;
+}
+EXPORT_SYMBOL_GPL(lpass_macro_get_codec_version);
+
 MODULE_DESCRIPTION("Common macro driver");
 MODULE_LICENSE("GPL");
diff --git a/sound/soc/codecs/lpass-macro-common.h b/sound/soc/codecs/lpass-macro-common.h
index d98718b3dc4b..f6f1bfe8eb77 100644
--- a/sound/soc/codecs/lpass-macro-common.h
+++ b/sound/soc/codecs/lpass-macro-common.h
@@ -18,6 +18,18 @@ enum lpass_version {
 	LPASS_VER_11_0_0,
 };
 
+enum lpass_codec_version {
+	LPASS_CODEC_VERSION_1_0 = 1,
+	LPASS_CODEC_VERSION_1_1,
+	LPASS_CODEC_VERSION_1_2,
+	LPASS_CODEC_VERSION_2_0,
+	LPASS_CODEC_VERSION_2_1,
+	LPASS_CODEC_VERSION_2_5,
+	LPASS_CODEC_VERSION_2_6,
+	LPASS_CODEC_VERSION_2_7,
+	LPASS_CODEC_VERSION_2_8,
+};
+
 struct lpass_macro {
 	struct device *macro_pd;
 	struct device *dcodec_pd;
@@ -25,5 +37,28 @@ struct lpass_macro {
 
 struct lpass_macro *lpass_macro_pds_init(struct device *dev);
 void lpass_macro_pds_exit(struct lpass_macro *pds);
+void lpass_macro_set_codec_version(int version);
+int lpass_macro_get_codec_version(void);
+
+static inline const char *lpass_macro_get_codec_version_string(int version)
+{
+	switch (version) {
+	case LPASS_CODEC_VERSION_2_0:
+		return "v2.0";
+	case LPASS_CODEC_VERSION_2_1:
+		return "v2.1";
+	case LPASS_CODEC_VERSION_2_5:
+		return "v2.5";
+	case LPASS_CODEC_VERSION_2_6:
+		return "v2.6";
+	case LPASS_CODEC_VERSION_2_7:
+		return "v2.7";
+	case LPASS_CODEC_VERSION_2_8:
+		return "v2.8";
+	default:
+		break;
+	}
+	return "NA";
+}
 
 #endif /* __LPASS_MACRO_COMMON_H__ */
diff --git a/sound/soc/codecs/lpass-va-macro.c b/sound/soc/codecs/lpass-va-macro.c
index db6272ee2df5..a94a1d93c19d 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -1462,6 +1462,33 @@ static int va_macro_validate_dmic_sample_rate(u32 dmic_sample_rate,
 	return dmic_sample_rate;
 }
 
+static void va_macro_set_lpass_codec_version(struct va_macro *va)
+{
+	int core_id_0 = 0, core_id_1 = 0, core_id_2 = 0, version;
+
+	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &core_id_0);
+	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &core_id_1);
+	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &core_id_2);
+
+	if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
+		version = LPASS_CODEC_VERSION_2_0;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0E))
+		version = LPASS_CODEC_VERSION_2_1;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x50 || core_id_2 == 0x51))
+		version = LPASS_CODEC_VERSION_2_5;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x60 || core_id_2 == 0x61))
+		version = LPASS_CODEC_VERSION_2_6;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x70 || core_id_2 == 0x71))
+		version = LPASS_CODEC_VERSION_2_7;
+	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
+		version = LPASS_CODEC_VERSION_2_8;
+
+	lpass_macro_set_codec_version(version);
+
+	dev_info(va->dev, "LPASS Codec Version %s\n",
+			lpass_macro_get_codec_version_string(version));
+}
+
 static int va_macro_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
@@ -1555,6 +1582,8 @@ static int va_macro_probe(struct platform_device *pdev)
 			goto err_npl;
 	}
 
+	va_macro_set_lpass_codec_version(va);
+
 	if (va->has_swr_master) {
 		/* Set default CLK div to 1 */
 		regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0,
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version
  2024-05-10 17:58 ` [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version srinivas.kandagatla
@ 2024-05-15 14:28   ` Dan Carpenter
  0 siblings, 0 replies; 6+ messages in thread
From: Dan Carpenter @ 2024-05-15 14:28 UTC (permalink / raw)
  To: oe-kbuild, srinivas.kandagatla, broonie
  Cc: lkp, oe-kbuild-all, perex, tiwai, alsa-devel, lgirdwood,
	linux-kernel, krzysztof.kozlowski, neil.armstrong,
	Srinivas Kandagatla

Hi,

kernel test robot noticed the following build warnings:

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/srinivas-kandagatla-linaro-org/ASoC-codecs-lpass-macro-add-helpers-to-get-codec-version/20240511-020042
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link:    https://lore.kernel.org/r/20240510175835.286775-2-srinivas.kandagatla%40linaro.org
patch subject: [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version
config: sparc-randconfig-r081-20240512 (https://download.01.org/0day-ci/archive/20240512/202405120735.qbbiUPaX-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 13.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202405120735.qbbiUPaX-lkp@intel.com/

smatch warnings:
sound/soc/codecs/lpass-va-macro.c:1485 va_macro_set_lpass_codec_version() error: uninitialized symbol 'version'.

vim +/version +1485 sound/soc/codecs/lpass-va-macro.c

787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1464  static void va_macro_set_lpass_codec_version(struct va_macro *va)
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1465  {
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1466  	int core_id_0 = 0, core_id_1 = 0, core_id_2 = 0, version;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1467  
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1468  	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_0, &core_id_0);
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1469  	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_1, &core_id_1);
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1470  	regmap_read(va->regmap, CDC_VA_TOP_CSR_CORE_ID_2, &core_id_2);
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1471  
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1472  	if ((core_id_0 == 0x01) && (core_id_1 == 0x0F))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1473  		version = LPASS_CODEC_VERSION_2_0;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1474  	if ((core_id_0 == 0x02) && (core_id_1 == 0x0E))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1475  		version = LPASS_CODEC_VERSION_2_1;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1476  	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x50 || core_id_2 == 0x51))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1477  		version = LPASS_CODEC_VERSION_2_5;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1478  	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x60 || core_id_2 == 0x61))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1479  		version = LPASS_CODEC_VERSION_2_6;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1480  	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x70 || core_id_2 == 0x71))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1481  		version = LPASS_CODEC_VERSION_2_7;
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1482  	if ((core_id_0 == 0x02) && (core_id_1 == 0x0F) && (core_id_2 == 0x80 || core_id_2 == 0x81))
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1483  		version = LPASS_CODEC_VERSION_2_8;

Uninitialized on else path.

787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1484  
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10 @1485  	lpass_macro_set_codec_version(version);
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1486  
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1487  	dev_info(va->dev, "LPASS Codec Version %s\n",
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1488  			lpass_macro_get_codec_version_string(version));
787a4e6d2bc156 Srinivas Kandagatla 2024-05-10  1489  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version
  2024-05-10 17:58 [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro srinivas.kandagatla
  2024-05-10 17:58 ` [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version srinivas.kandagatla
@ 2024-05-10 17:58 ` srinivas.kandagatla
  2024-05-15 14:30   ` Dan Carpenter
  2024-06-17 17:26 ` [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro Mark Brown
  2 siblings, 1 reply; 6+ messages in thread
From: srinivas.kandagatla @ 2024-05-10 17:58 UTC (permalink / raw)
  To: broonie
  Cc: perex, tiwai, alsa-devel, lgirdwood, linux-kernel,
	krzysztof.kozlowski, neil.armstrong, Srinivas Kandagatla

From: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>

LPASS Codec v2.6 has significant changes in the rx register offsets.
Due to this headset playback on SM8550, SM8650, x1e80100 and all SoCs
after SM8450 have only Left working.

This patch adjusts the registers to accomdate 2.6 changes. With this
fixed now L and R are functional on Headset playback.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
---
 sound/soc/codecs/lpass-rx-macro.c | 565 ++++++++++++++++++++++--------
 1 file changed, 410 insertions(+), 155 deletions(-)

diff --git a/sound/soc/codecs/lpass-rx-macro.c b/sound/soc/codecs/lpass-rx-macro.c
index f35187d69cac..c1724f0830e9 100644
--- a/sound/soc/codecs/lpass-rx-macro.c
+++ b/sound/soc/codecs/lpass-rx-macro.c
@@ -158,7 +158,7 @@
 #define CDC_RX_INTR_CTRL_LEVEL0		(0x03C0)
 #define CDC_RX_INTR_CTRL_BYPASS0	(0x03C8)
 #define CDC_RX_INTR_CTRL_SET0		(0x03D0)
-#define CDC_RX_RXn_RX_PATH_CTL(n)	(0x0400 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CTL(rx, n)	(0x0400  + rx->rxn_reg_offset * n)
 #define CDC_RX_RX0_RX_PATH_CTL		(0x0400)
 #define CDC_RX_PATH_RESET_EN_MASK	BIT(6)
 #define CDC_RX_PATH_CLK_EN_MASK		BIT(5)
@@ -166,45 +166,47 @@
 #define CDC_RX_PATH_PGA_MUTE_MASK	BIT(4)
 #define CDC_RX_PATH_PGA_MUTE_ENABLE	BIT(4)
 #define CDC_RX_PATH_PCM_RATE_MASK	GENMASK(3, 0)
-#define CDC_RX_RXn_RX_PATH_CFG0(n)	(0x0404 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG0(rx, n)	(0x0404  + rx->rxn_reg_offset * n)
 #define CDC_RX_RXn_COMP_EN_MASK		BIT(1)
 #define CDC_RX_RX0_RX_PATH_CFG0		(0x0404)
 #define CDC_RX_RXn_CLSH_EN_MASK		BIT(6)
 #define CDC_RX_DLY_ZN_EN_MASK		BIT(3)
 #define CDC_RX_DLY_ZN_ENABLE		BIT(3)
 #define CDC_RX_RXn_HD2_EN_MASK		BIT(2)
-#define CDC_RX_RXn_RX_PATH_CFG1(n)	(0x0408 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG1(rx, n)	(0x0408  + rx->rxn_reg_offset * n)
 #define CDC_RX_RXn_SIDETONE_EN_MASK	BIT(4)
 #define CDC_RX_RX0_RX_PATH_CFG1		(0x0408)
 #define CDC_RX_RX0_HPH_L_EAR_SEL_MASK	BIT(1)
-#define CDC_RX_RXn_RX_PATH_CFG2(n)	(0x040C + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG2(rx, n)	(0x040C  + rx->rxn_reg_offset * n)
 #define CDC_RX_RXn_HPF_CUT_FREQ_MASK	GENMASK(1, 0)
 #define CDC_RX_RX0_RX_PATH_CFG2		(0x040C)
-#define CDC_RX_RXn_RX_PATH_CFG3(n)	(0x0410 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_CFG3(rx, n)	(0x0410  + rx->rxn_reg_offset * n)
 #define CDC_RX_RX0_RX_PATH_CFG3		(0x0410)
 #define CDC_RX_DC_COEFF_SEL_MASK	GENMASK(1, 0)
 #define CDC_RX_DC_COEFF_SEL_TWO		0x2
-#define CDC_RX_RXn_RX_VOL_CTL(n)	(0x0414 + 0x80 * n)
+#define CDC_RX_RXn_RX_VOL_CTL(rx, n)	(0x0414  + rx->rxn_reg_offset * n)
 #define CDC_RX_RX0_RX_VOL_CTL		(0x0414)
-#define CDC_RX_RXn_RX_PATH_MIX_CTL(n)	(0x0418 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_MIX_CTL(rx, n)	(0x0418  + rx->rxn_reg_offset * n)
 #define CDC_RX_RXn_MIX_PCM_RATE_MASK	GENMASK(3, 0)
 #define CDC_RX_RXn_MIX_RESET_MASK	BIT(6)
 #define CDC_RX_RXn_MIX_RESET		BIT(6)
 #define CDC_RX_RXn_MIX_CLK_EN_MASK	BIT(5)
 #define CDC_RX_RX0_RX_PATH_MIX_CTL	(0x0418)
 #define CDC_RX_RX0_RX_PATH_MIX_CFG	(0x041C)
-#define CDC_RX_RXn_RX_VOL_MIX_CTL(n)	(0x0420 + 0x80 * n)
+#define CDC_RX_RXn_RX_VOL_MIX_CTL(rx, n)	(0x0420  + rx->rxn_reg_offset * n)
 #define CDC_RX_RX0_RX_VOL_MIX_CTL	(0x0420)
 #define CDC_RX_RX0_RX_PATH_SEC1		(0x0424)
 #define CDC_RX_RX0_RX_PATH_SEC2		(0x0428)
 #define CDC_RX_RX0_RX_PATH_SEC3		(0x042C)
+#define CDC_RX_RXn_RX_PATH_SEC3(rx, n)	(0x042c  + rx->rxn_reg_offset * n)
 #define CDC_RX_RX0_RX_PATH_SEC4		(0x0430)
 #define CDC_RX_RX0_RX_PATH_SEC7		(0x0434)
+#define CDC_RX_RXn_RX_PATH_SEC7(rx, n)	(0x0434  + rx->rxn_reg_offset * n)
 #define CDC_RX_DSM_OUT_DELAY_SEL_MASK	GENMASK(2, 0)
 #define CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE	0x2
 #define CDC_RX_RX0_RX_PATH_MIX_SEC0	(0x0438)
 #define CDC_RX_RX0_RX_PATH_MIX_SEC1	(0x043C)
-#define CDC_RX_RXn_RX_PATH_DSM_CTL(n)	(0x0440 + 0x80 * n)
+#define CDC_RX_RXn_RX_PATH_DSM_CTL(rx, n)	(0x0440  + rx->rxn_reg_offset * n)
 #define CDC_RX_RXn_DSM_CLK_EN_MASK	BIT(0)
 #define CDC_RX_RX0_RX_PATH_DSM_CTL	(0x0440)
 #define CDC_RX_RX0_RX_PATH_DSM_DATA1	(0x0444)
@@ -213,6 +215,7 @@
 #define CDC_RX_RX0_RX_PATH_DSM_DATA4	(0x0450)
 #define CDC_RX_RX0_RX_PATH_DSM_DATA5	(0x0454)
 #define CDC_RX_RX0_RX_PATH_DSM_DATA6	(0x0458)
+/* RX offsets prior to 2.6 codec version */
 #define CDC_RX_RX1_RX_PATH_CTL		(0x0480)
 #define CDC_RX_RX1_RX_PATH_CFG0		(0x0484)
 #define CDC_RX_RX1_RX_PATH_CFG1		(0x0488)
@@ -259,10 +262,58 @@
 #define CDC_RX_RX2_RX_PATH_MIX_SEC0	(0x0544)
 #define CDC_RX_RX2_RX_PATH_MIX_SEC1	(0x0548)
 #define CDC_RX_RX2_RX_PATH_DSM_CTL	(0x054C)
+
+/* LPASS CODEC version 2.6 rx reg offsets */
+#define CDC_2_6_RX_RX1_RX_PATH_CTL		(0x04c0)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG0		(0x04c4)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG1		(0x04c8)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG2		(0x04cC)
+#define CDC_2_6_RX_RX1_RX_PATH_CFG3		(0x04d0)
+#define CDC_2_6_RX_RX1_RX_VOL_CTL		(0x04d4)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_CTL		(0x04d8)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_CFG		(0x04dC)
+#define CDC_2_6_RX_RX1_RX_VOL_MIX_CTL		(0x04e0)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC1		(0x04e4)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC2		(0x04e8)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC3		(0x04eC)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC4		(0x04f0)
+#define CDC_2_6_RX_RX1_RX_PATH_SEC7		(0x04f4)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0		(0x04f8)
+#define CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1		(0x04fC)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_CTL		(0x0500)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1	(0x0504)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2	(0x0508)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3	(0x050C)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4	(0x0510)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5	(0x0514)
+#define CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6	(0x0518)
+
+#define CDC_2_6_RX_RX2_RX_PATH_CTL		(0x0580)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG0		(0x0584)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG1		(0x0588)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG2		(0x058C)
+#define CDC_2_6_RX_RX2_RX_PATH_CFG3		(0x0590)
+#define CDC_2_6_RX_RX2_RX_VOL_CTL		(0x0594)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_CTL		(0x0598)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_CFG		(0x059C)
+#define CDC_2_6_RX_RX2_RX_VOL_MIX_CTL		(0x05a0)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC0		(0x05a4)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC1		(0x05a8)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC2		(0x05aC)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC3		(0x05b0)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC4		(0x05b4)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC5		(0x05b8)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC6		(0x05bC)
+#define CDC_2_6_RX_RX2_RX_PATH_SEC7		(0x05c0)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0		(0x05c4)
+#define CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1		(0x05c8)
+#define CDC_2_6_RX_RX2_RX_PATH_DSM_CTL		(0x05cC)
+
 #define CDC_RX_IDLE_DETECT_PATH_CTL	(0x0780)
 #define CDC_RX_IDLE_DETECT_CFG0		(0x0784)
 #define CDC_RX_IDLE_DETECT_CFG1		(0x0788)
 #define CDC_RX_IDLE_DETECT_CFG2		(0x078C)
+
 #define CDC_RX_IDLE_DETECT_CFG3		(0x0790)
 #define CDC_RX_COMPANDERn_CTL0(n)	(0x0800 + 0x40 * n)
 #define CDC_RX_COMPANDERn_CLK_EN_MASK	BIT(0)
@@ -598,6 +649,8 @@ struct rx_macro {
 	int rx_mclk_users;
 	int clsh_users;
 	int rx_mclk_cnt;
+	int codec_version;
+	int rxn_reg_offset;
 	bool is_ear_mode_on;
 	bool hph_pwr_mode;
 	bool hph_hd2_mode;
@@ -755,11 +808,15 @@ static SOC_ENUM_SINGLE_DECL(rx_int1_2_interp_enum, SND_SOC_NOPM, 0,
 			    rx_int1_2_interp_mux_text);
 static SOC_ENUM_SINGLE_DECL(rx_int2_2_interp_enum, SND_SOC_NOPM, 0,
 			    rx_int2_2_interp_mux_text);
+
 static SOC_ENUM_SINGLE_DECL(rx_int0_dem_inp_enum, CDC_RX_RX0_RX_PATH_CFG1, 0,
 			    rx_int_dem_inp_mux_text);
 static SOC_ENUM_SINGLE_DECL(rx_int1_dem_inp_enum, CDC_RX_RX1_RX_PATH_CFG1, 0,
 			    rx_int_dem_inp_mux_text);
 
+static SOC_ENUM_SINGLE_DECL(rx_2_6_int1_dem_inp_enum, CDC_2_6_RX_RX1_RX_PATH_CFG1, 0,
+			    rx_int_dem_inp_mux_text);
+
 static SOC_ENUM_SINGLE_DECL(rx_macro_rx0_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 static SOC_ENUM_SINGLE_DECL(rx_macro_rx1_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
 static SOC_ENUM_SINGLE_DECL(rx_macro_rx2_enum, SND_SOC_NOPM, 0, rx_macro_mux_text);
@@ -976,49 +1033,6 @@ static const struct reg_default rx_defaults[] = {
 	{ CDC_RX_RX0_RX_PATH_DSM_DATA4, 0x55 },
 	{ CDC_RX_RX0_RX_PATH_DSM_DATA5, 0x55 },
 	{ CDC_RX_RX0_RX_PATH_DSM_DATA6, 0x55 },
-	{ CDC_RX_RX1_RX_PATH_CTL, 0x04 },
-	{ CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
-	{ CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
-	{ CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
-	{ CDC_RX_RX1_RX_VOL_CTL, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
-	{ CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
-	{ CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
-	{ CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
-	{ CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
-	{ CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
-	{ CDC_RX_RX2_RX_PATH_CTL, 0x04 },
-	{ CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
-	{ CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
-	{ CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
-	{ CDC_RX_RX2_RX_VOL_CTL, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
-	{ CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
-	{ CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
-	{ CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
-	{ CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
-	{ CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
-	{ CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
 	{ CDC_RX_IDLE_DETECT_PATH_CTL, 0x00 },
 	{ CDC_RX_IDLE_DETECT_CFG0, 0x07 },
 	{ CDC_RX_IDLE_DETECT_CFG1, 0x3C },
@@ -1121,6 +1135,99 @@ static const struct reg_default rx_defaults[] = {
 	{ CDC_RX_DSD1_CFG2, 0x96 },
 };
 
+static const struct reg_default rx_2_6_defaults[] = {
+	{ CDC_2_6_RX_RX1_RX_PATH_CTL, 0x04 },
+	{ CDC_2_6_RX_RX1_RX_PATH_CFG0, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_CFG1, 0x64 },
+	{ CDC_2_6_RX_RX1_RX_PATH_CFG2, 0x8F },
+	{ CDC_2_6_RX_RX1_RX_PATH_CFG3, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_VOL_CTL, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
+	{ CDC_2_6_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
+	{ CDC_2_6_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_SEC1, 0x08 },
+	{ CDC_2_6_RX_RX1_RX_PATH_SEC2, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_SEC3, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_SEC4, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_SEC7, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
+	{ CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
+	{ CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
+	{ CDC_2_6_RX_RX2_RX_PATH_CTL, 0x04 },
+	{ CDC_2_6_RX_RX2_RX_PATH_CFG0, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_CFG1, 0x64 },
+	{ CDC_2_6_RX_RX2_RX_PATH_CFG2, 0x8F },
+	{ CDC_2_6_RX_RX2_RX_PATH_CFG3, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_VOL_CTL, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
+	{ CDC_2_6_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
+	{ CDC_2_6_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC0, 0x04 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC1, 0x08 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC2, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC3, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC4, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC5, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC6, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_SEC7, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
+	{ CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
+	{ CDC_2_6_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
+};
+
+static const struct reg_default rx_pre_2_6_defaults[] = {
+	{ CDC_RX_RX1_RX_PATH_CTL, 0x04 },
+	{ CDC_RX_RX1_RX_PATH_CFG0, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_CFG1, 0x64 },
+	{ CDC_RX_RX1_RX_PATH_CFG2, 0x8F },
+	{ CDC_RX_RX1_RX_PATH_CFG3, 0x00 },
+	{ CDC_RX_RX1_RX_VOL_CTL, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_MIX_CTL, 0x04 },
+	{ CDC_RX_RX1_RX_PATH_MIX_CFG, 0x7E },
+	{ CDC_RX_RX1_RX_VOL_MIX_CTL, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_SEC1, 0x08 },
+	{ CDC_RX_RX1_RX_PATH_SEC2, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_SEC3, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_SEC4, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_SEC7, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_MIX_SEC0, 0x08 },
+	{ CDC_RX_RX1_RX_PATH_MIX_SEC1, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_DSM_CTL, 0x08 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA1, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA2, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA3, 0x00 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA4, 0x55 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA5, 0x55 },
+	{ CDC_RX_RX1_RX_PATH_DSM_DATA6, 0x55 },
+	{ CDC_RX_RX2_RX_PATH_CTL, 0x04 },
+	{ CDC_RX_RX2_RX_PATH_CFG0, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_CFG1, 0x64 },
+	{ CDC_RX_RX2_RX_PATH_CFG2, 0x8F },
+	{ CDC_RX_RX2_RX_PATH_CFG3, 0x00 },
+	{ CDC_RX_RX2_RX_VOL_CTL, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_MIX_CTL, 0x04 },
+	{ CDC_RX_RX2_RX_PATH_MIX_CFG, 0x7E },
+	{ CDC_RX_RX2_RX_VOL_MIX_CTL, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC0, 0x04 },
+	{ CDC_RX_RX2_RX_PATH_SEC1, 0x08 },
+	{ CDC_RX_RX2_RX_PATH_SEC2, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC3, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC4, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC5, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC6, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_SEC7, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_MIX_SEC0, 0x08 },
+	{ CDC_RX_RX2_RX_PATH_MIX_SEC1, 0x00 },
+	{ CDC_RX_RX2_RX_PATH_DSM_CTL, 0x00 },
+
+};
+
 static bool rx_is_wronly_register(struct device *dev,
 					unsigned int reg)
 {
@@ -1175,8 +1282,114 @@ static bool rx_is_volatile_register(struct device *dev, unsigned int reg)
 	return false;
 }
 
+static bool rx_2_2_is_rw_register(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case CDC_RX_RX1_RX_PATH_CTL:
+	case CDC_RX_RX1_RX_PATH_CFG0:
+	case CDC_RX_RX1_RX_PATH_CFG1:
+	case CDC_RX_RX1_RX_PATH_CFG2:
+	case CDC_RX_RX1_RX_PATH_CFG3:
+	case CDC_RX_RX1_RX_VOL_CTL:
+	case CDC_RX_RX1_RX_PATH_MIX_CTL:
+	case CDC_RX_RX1_RX_PATH_MIX_CFG:
+	case CDC_RX_RX1_RX_VOL_MIX_CTL:
+	case CDC_RX_RX1_RX_PATH_SEC1:
+	case CDC_RX_RX1_RX_PATH_SEC2:
+	case CDC_RX_RX1_RX_PATH_SEC3:
+	case CDC_RX_RX1_RX_PATH_SEC4:
+	case CDC_RX_RX1_RX_PATH_SEC7:
+	case CDC_RX_RX1_RX_PATH_MIX_SEC0:
+	case CDC_RX_RX1_RX_PATH_MIX_SEC1:
+	case CDC_RX_RX1_RX_PATH_DSM_CTL:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA1:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA2:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA3:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA4:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA5:
+	case CDC_RX_RX1_RX_PATH_DSM_DATA6:
+	case CDC_RX_RX2_RX_PATH_CTL:
+	case CDC_RX_RX2_RX_PATH_CFG0:
+	case CDC_RX_RX2_RX_PATH_CFG1:
+	case CDC_RX_RX2_RX_PATH_CFG2:
+	case CDC_RX_RX2_RX_PATH_CFG3:
+	case CDC_RX_RX2_RX_VOL_CTL:
+	case CDC_RX_RX2_RX_PATH_MIX_CTL:
+	case CDC_RX_RX2_RX_PATH_MIX_CFG:
+	case CDC_RX_RX2_RX_VOL_MIX_CTL:
+	case CDC_RX_RX2_RX_PATH_SEC0:
+	case CDC_RX_RX2_RX_PATH_SEC1:
+	case CDC_RX_RX2_RX_PATH_SEC2:
+	case CDC_RX_RX2_RX_PATH_SEC3:
+	case CDC_RX_RX2_RX_PATH_SEC4:
+	case CDC_RX_RX2_RX_PATH_SEC5:
+	case CDC_RX_RX2_RX_PATH_SEC6:
+	case CDC_RX_RX2_RX_PATH_SEC7:
+	case CDC_RX_RX2_RX_PATH_MIX_SEC0:
+	case CDC_RX_RX2_RX_PATH_MIX_SEC1:
+	case CDC_RX_RX2_RX_PATH_DSM_CTL:
+		return true;
+	}
+
+	return false;
+}
+
+static bool rx_2_6_is_rw_register(struct device *dev, unsigned int reg)
+{
+	switch (reg) {
+	case CDC_2_6_RX_RX1_RX_PATH_CTL:
+	case CDC_2_6_RX_RX1_RX_PATH_CFG0:
+	case CDC_2_6_RX_RX1_RX_PATH_CFG1:
+	case CDC_2_6_RX_RX1_RX_PATH_CFG2:
+	case CDC_2_6_RX_RX1_RX_PATH_CFG3:
+	case CDC_2_6_RX_RX1_RX_VOL_CTL:
+	case CDC_2_6_RX_RX1_RX_PATH_MIX_CTL:
+	case CDC_2_6_RX_RX1_RX_PATH_MIX_CFG:
+	case CDC_2_6_RX_RX1_RX_VOL_MIX_CTL:
+	case CDC_2_6_RX_RX1_RX_PATH_SEC1:
+	case CDC_2_6_RX_RX1_RX_PATH_SEC2:
+	case CDC_2_6_RX_RX1_RX_PATH_SEC3:
+	case CDC_2_6_RX_RX1_RX_PATH_SEC4:
+	case CDC_2_6_RX_RX1_RX_PATH_SEC7:
+	case CDC_2_6_RX_RX1_RX_PATH_MIX_SEC0:
+	case CDC_2_6_RX_RX1_RX_PATH_MIX_SEC1:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_CTL:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA1:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA2:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA3:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA4:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA5:
+	case CDC_2_6_RX_RX1_RX_PATH_DSM_DATA6:
+	case CDC_2_6_RX_RX2_RX_PATH_CTL:
+	case CDC_2_6_RX_RX2_RX_PATH_CFG0:
+	case CDC_2_6_RX_RX2_RX_PATH_CFG1:
+	case CDC_2_6_RX_RX2_RX_PATH_CFG2:
+	case CDC_2_6_RX_RX2_RX_PATH_CFG3:
+	case CDC_2_6_RX_RX2_RX_VOL_CTL:
+	case CDC_2_6_RX_RX2_RX_PATH_MIX_CTL:
+	case CDC_2_6_RX_RX2_RX_PATH_MIX_CFG:
+	case CDC_2_6_RX_RX2_RX_VOL_MIX_CTL:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC0:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC1:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC2:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC3:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC4:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC5:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC6:
+	case CDC_2_6_RX_RX2_RX_PATH_SEC7:
+	case CDC_2_6_RX_RX2_RX_PATH_MIX_SEC0:
+	case CDC_2_6_RX_RX2_RX_PATH_MIX_SEC1:
+	case CDC_2_6_RX_RX2_RX_PATH_DSM_CTL:
+		return true;
+	}
+
+	return false;
+}
+
 static bool rx_is_rw_register(struct device *dev, unsigned int reg)
 {
+	struct rx_macro *rx = dev_get_drvdata(dev);
+
 	switch (reg) {
 	case CDC_RX_TOP_TOP_CFG0:
 	case CDC_RX_TOP_SWR_CTRL:
@@ -1306,49 +1519,6 @@ static bool rx_is_rw_register(struct device *dev, unsigned int reg)
 	case CDC_RX_RX0_RX_PATH_DSM_DATA4:
 	case CDC_RX_RX0_RX_PATH_DSM_DATA5:
 	case CDC_RX_RX0_RX_PATH_DSM_DATA6:
-	case CDC_RX_RX1_RX_PATH_CTL:
-	case CDC_RX_RX1_RX_PATH_CFG0:
-	case CDC_RX_RX1_RX_PATH_CFG1:
-	case CDC_RX_RX1_RX_PATH_CFG2:
-	case CDC_RX_RX1_RX_PATH_CFG3:
-	case CDC_RX_RX1_RX_VOL_CTL:
-	case CDC_RX_RX1_RX_PATH_MIX_CTL:
-	case CDC_RX_RX1_RX_PATH_MIX_CFG:
-	case CDC_RX_RX1_RX_VOL_MIX_CTL:
-	case CDC_RX_RX1_RX_PATH_SEC1:
-	case CDC_RX_RX1_RX_PATH_SEC2:
-	case CDC_RX_RX1_RX_PATH_SEC3:
-	case CDC_RX_RX1_RX_PATH_SEC4:
-	case CDC_RX_RX1_RX_PATH_SEC7:
-	case CDC_RX_RX1_RX_PATH_MIX_SEC0:
-	case CDC_RX_RX1_RX_PATH_MIX_SEC1:
-	case CDC_RX_RX1_RX_PATH_DSM_CTL:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA1:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA2:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA3:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA4:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA5:
-	case CDC_RX_RX1_RX_PATH_DSM_DATA6:
-	case CDC_RX_RX2_RX_PATH_CTL:
-	case CDC_RX_RX2_RX_PATH_CFG0:
-	case CDC_RX_RX2_RX_PATH_CFG1:
-	case CDC_RX_RX2_RX_PATH_CFG2:
-	case CDC_RX_RX2_RX_PATH_CFG3:
-	case CDC_RX_RX2_RX_VOL_CTL:
-	case CDC_RX_RX2_RX_PATH_MIX_CTL:
-	case CDC_RX_RX2_RX_PATH_MIX_CFG:
-	case CDC_RX_RX2_RX_VOL_MIX_CTL:
-	case CDC_RX_RX2_RX_PATH_SEC0:
-	case CDC_RX_RX2_RX_PATH_SEC1:
-	case CDC_RX_RX2_RX_PATH_SEC2:
-	case CDC_RX_RX2_RX_PATH_SEC3:
-	case CDC_RX_RX2_RX_PATH_SEC4:
-	case CDC_RX_RX2_RX_PATH_SEC5:
-	case CDC_RX_RX2_RX_PATH_SEC6:
-	case CDC_RX_RX2_RX_PATH_SEC7:
-	case CDC_RX_RX2_RX_PATH_MIX_SEC0:
-	case CDC_RX_RX2_RX_PATH_MIX_SEC1:
-	case CDC_RX_RX2_RX_PATH_DSM_CTL:
 	case CDC_RX_IDLE_DETECT_PATH_CTL:
 	case CDC_RX_IDLE_DETECT_CFG0:
 	case CDC_RX_IDLE_DETECT_CFG1:
@@ -1435,7 +1605,10 @@ static bool rx_is_rw_register(struct device *dev, unsigned int reg)
 		return true;
 	}
 
-	return false;
+	if (rx->codec_version == LPASS_CODEC_VERSION_2_6)
+		return rx_2_6_is_rw_register(dev, reg);
+
+	return rx_2_2_is_rw_register(dev, reg);
 }
 
 static bool rx_is_writeable_register(struct device *dev, unsigned int reg)
@@ -1485,14 +1658,12 @@ static bool rx_is_readable_register(struct device *dev, unsigned int reg)
 	return rx_is_rw_register(dev, reg);
 }
 
-static const struct regmap_config rx_regmap_config = {
+static struct regmap_config rx_regmap_config = {
 	.name = "rx_macro",
 	.reg_bits = 16,
 	.val_bits = 32, /* 8 but with 32 bit read/write */
 	.reg_stride = 4,
 	.cache_type = REGCACHE_FLAT,
-	.reg_defaults = rx_defaults,
-	.num_reg_defaults = ARRAY_SIZE(rx_defaults),
 	.max_register = RX_MAX_OFFSET,
 	.writeable_reg = rx_is_writeable_register,
 	.volatile_reg = rx_is_volatile_register,
@@ -1504,16 +1675,17 @@ static int rx_macro_int_dem_inp_mux_put(struct snd_kcontrol *kcontrol,
 {
 	struct snd_soc_dapm_widget *widget = snd_soc_dapm_kcontrol_widget(kcontrol);
 	struct snd_soc_component *component = snd_soc_dapm_to_component(widget->dapm);
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 	unsigned short look_ahead_dly_reg;
 	unsigned int val;
 
 	val = ucontrol->value.enumerated.item[0];
 
-	if (e->reg == CDC_RX_RX0_RX_PATH_CFG1)
-		look_ahead_dly_reg = CDC_RX_RX0_RX_PATH_CFG0;
-	else if (e->reg == CDC_RX_RX1_RX_PATH_CFG1)
-		look_ahead_dly_reg = CDC_RX_RX1_RX_PATH_CFG0;
+	if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 0))
+		look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
+	else if (e->reg == CDC_RX_RXn_RX_PATH_CFG1(rx, 1))
+		look_ahead_dly_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
 
 	/* Set Look Ahead Delay */
 	if (val)
@@ -1534,6 +1706,10 @@ static const struct snd_kcontrol_new rx_int1_dem_inp_mux =
 		SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_int1_dem_inp_enum,
 		  snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
 
+static const struct snd_kcontrol_new rx_2_6_int1_dem_inp_mux =
+		SOC_DAPM_ENUM_EXT("rx_int1_dem_inp", rx_2_6_int1_dem_inp_enum,
+		  snd_soc_dapm_get_enum_double, rx_macro_int_dem_inp_mux_put);
+
 static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
 					       int rate_reg_val, u32 sample_rate)
 {
@@ -1567,7 +1743,7 @@ static int rx_macro_set_prim_interpolator_rate(struct snd_soc_dai *dai,
 			if ((inp0_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
 			    (inp1_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0) ||
 			    (inp2_sel == int_1_mix1_inp + INTn_1_INP_SEL_RX0)) {
-				int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(j);
+				int_fs_reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
 				/* sample_rate is in Hz */
 				snd_soc_component_update_bits(component, int_fs_reg,
 							      CDC_RX_PATH_PCM_RATE_MASK,
@@ -1600,7 +1776,7 @@ static int rx_macro_set_mix_interpolator_rate(struct snd_soc_dai *dai,
 									CDC_RX_INTX_2_SEL_MASK);
 
 			if (int_mux_cfg1_val == int_2_inp + INTn_2_INP_SEL_RX0) {
-				int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
+				int_fs_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
 				snd_soc_component_update_bits(component, int_fs_reg,
 							      CDC_RX_RXn_MIX_PCM_RATE_MASK,
 							      rate_reg_val);
@@ -1719,6 +1895,7 @@ static int rx_macro_get_channel_map(struct snd_soc_dai *dai,
 static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
 {
 	struct snd_soc_component *component = dai->component;
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 	uint16_t j, reg, mix_reg, dsm_reg;
 	u16 int_mux_cfg0, int_mux_cfg1;
 	u8 int_mux_cfg0_val, int_mux_cfg1_val;
@@ -1729,9 +1906,9 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
 	case RX_MACRO_AIF3_PB:
 	case RX_MACRO_AIF4_PB:
 		for (j = 0; j < INTERP_MAX; j++) {
-			reg = CDC_RX_RXn_RX_PATH_CTL(j);
-			mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(j);
-			dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(j);
+			reg = CDC_RX_RXn_RX_PATH_CTL(rx, j);
+			mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, j);
+			dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, j);
 
 			if (mute) {
 				snd_soc_component_update_bits(component, reg,
@@ -1748,7 +1925,7 @@ static int rx_macro_digital_mute(struct snd_soc_dai *dai, int mute, int stream)
 			}
 
 			if (j == INTERP_AUX)
-				dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
+				dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2);
 
 			int_mux_cfg0 = CDC_RX_INP_MUX_RX_INT0_CFG0 + j * 8;
 			int_mux_cfg1 = int_mux_cfg0 + 4;
@@ -1956,10 +2133,11 @@ static int rx_macro_enable_main_path(struct snd_soc_dapm_widget *w,
 					int event)
 {
 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 	u16 gain_reg, reg;
 
-	reg = CDC_RX_RXn_RX_PATH_CTL(w->shift);
-	gain_reg = CDC_RX_RXn_RX_VOL_CTL(w->shift);
+	reg = CDC_RX_RXn_RX_PATH_CTL(rx, w->shift);
+	gain_reg = CDC_RX_RXn_RX_VOL_CTL(rx, w->shift);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
@@ -1991,7 +2169,7 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
 	if (comp == INTERP_AUX)
 		return 0;
 
-	pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(comp)) & 0x0F;
+	pcm_rate = snd_soc_component_read(component, CDC_RX_RXn_RX_PATH_CTL(rx, comp)) & 0x0F;
 	if (pcm_rate < 0x06)
 		val = 0x03;
 	else if (pcm_rate < 0x08)
@@ -2002,11 +2180,11 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
 		val = 0x00;
 
 	if (SND_SOC_DAPM_EVENT_ON(event))
-		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
+		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
 					      CDC_RX_DC_COEFF_SEL_MASK, val);
 
 	if (SND_SOC_DAPM_EVENT_OFF(event))
-		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(comp),
+		snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, comp),
 					      CDC_RX_DC_COEFF_SEL_MASK, 0x3);
 	if (!rx->comp_enabled[comp])
 		return 0;
@@ -2019,14 +2197,14 @@ static int rx_macro_config_compander(struct snd_soc_component *component,
 					      CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x1);
 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
 					      CDC_RX_COMPANDERn_SOFT_RST_MASK, 0x0);
-		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
+		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
 					      CDC_RX_RXn_COMP_EN_MASK, 0x1);
 	}
 
 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
 					      CDC_RX_COMPANDERn_HALT_MASK, 0x1);
-		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(comp),
+		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG0(rx, comp),
 					      CDC_RX_RXn_COMP_EN_MASK, 0x0);
 		snd_soc_component_write_field(component, CDC_RX_COMPANDERn_CTL0(comp),
 					      CDC_RX_COMPANDERn_CLK_EN_MASK, 0x0);
@@ -2125,13 +2303,13 @@ static int rx_macro_config_aux_hpf(struct snd_soc_component *component,
 		/* Update Aux HPF control */
 		if (!rx->is_aux_hpf_on)
 			snd_soc_component_update_bits(component,
-				CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x00);
+				CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x00);
 	}
 
 	if (SND_SOC_DAPM_EVENT_OFF(event)) {
 		/* Reset to default (HPF=ON) */
 		snd_soc_component_update_bits(component,
-			CDC_RX_RX2_RX_PATH_CFG1, 0x04, 0x04);
+			CDC_RX_RXn_RX_PATH_CFG1(rx, 2), 0x04, 0x04);
 	}
 
 	return 0;
@@ -2157,7 +2335,6 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
 
 	if (!SND_SOC_DAPM_EVENT_ON(event))
 		return 0;
-
 	rx_macro_enable_clsh_block(rx, true);
 	if (interp_n == INTERP_HPHL ||
 		interp_n == INTERP_HPHR) {
@@ -2183,7 +2360,7 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
 				CDC_RX_CLSH_DECAY_CTRL,
 				CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
 		snd_soc_component_write_field(component,
-				CDC_RX_RX0_RX_PATH_CFG0,
+				CDC_RX_RXn_RX_PATH_CFG0(rx, 0),
 				CDC_RX_RXn_CLSH_EN_MASK, 0x1);
 		break;
 	case INTERP_HPHR:
@@ -2199,15 +2376,15 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
 				CDC_RX_CLSH_DECAY_CTRL,
 				CDC_RX_CLSH_DECAY_RATE_MASK, 0x0);
 		snd_soc_component_write_field(component,
-				CDC_RX_RX1_RX_PATH_CFG0,
+				CDC_RX_RXn_RX_PATH_CFG0(rx, 1),
 				CDC_RX_RXn_CLSH_EN_MASK, 0x1);
 		break;
 	case INTERP_AUX:
 		snd_soc_component_update_bits(component,
-				CDC_RX_RX2_RX_PATH_CFG0,
+				CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
 				CDC_RX_RX2_DLY_Z_EN_MASK, 1);
 		snd_soc_component_write_field(component,
-				CDC_RX_RX2_RX_PATH_CFG0,
+				CDC_RX_RXn_RX_PATH_CFG0(rx, 2),
 				CDC_RX_RX2_CLSH_EN_MASK, 1);
 		break;
 	}
@@ -2218,16 +2395,17 @@ static int rx_macro_config_classh(struct snd_soc_component *component,
 static void rx_macro_hd2_control(struct snd_soc_component *component,
 				 u16 interp_idx, int event)
 {
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 	u16 hd2_scale_reg, hd2_enable_reg;
 
 	switch (interp_idx) {
 	case INTERP_HPHL:
-		hd2_scale_reg = CDC_RX_RX0_RX_PATH_SEC3;
-		hd2_enable_reg = CDC_RX_RX0_RX_PATH_CFG0;
+		hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 0);
+		hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 0);
 		break;
 	case INTERP_HPHR:
-		hd2_scale_reg = CDC_RX_RX1_RX_PATH_SEC3;
-		hd2_enable_reg = CDC_RX_RX1_RX_PATH_CFG0;
+		hd2_scale_reg = CDC_RX_RXn_RX_PATH_SEC3(rx, 1);
+		hd2_enable_reg = CDC_RX_RXn_RX_PATH_CFG0(rx, 1);
 		break;
 	}
 
@@ -2482,7 +2660,7 @@ static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
 		if (interp_idx == INTERP_HPHL) {
 			if (rx->is_ear_mode_on)
 				snd_soc_component_write_field(component,
-					CDC_RX_RX0_RX_PATH_CFG1,
+					CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
 					CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x1);
 			else
 				snd_soc_component_write_field(component,
@@ -2499,7 +2677,7 @@ static int rx_macro_hphdelay_lutbypass(struct snd_soc_component *component,
 
 	if (hph_lut_bypass_reg && SND_SOC_DAPM_EVENT_OFF(event)) {
 		snd_soc_component_write_field(component,
-					CDC_RX_RX0_RX_PATH_CFG1,
+					CDC_RX_RXn_RX_PATH_CFG1(rx, 0),
 					CDC_RX_RX0_HPH_L_EAR_SEL_MASK, 0x0);
 		snd_soc_component_update_bits(component, hph_lut_bypass_reg,
 					CDC_RX_TOP_HPH_LUT_BYPASS_MASK, 0);
@@ -2516,11 +2694,13 @@ static int rx_macro_enable_interp_clk(struct snd_soc_component *component,
 	u16 main_reg, dsm_reg, rx_cfg2_reg;
 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 
-	main_reg = CDC_RX_RXn_RX_PATH_CTL(interp_idx);
-	dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(interp_idx);
+	main_reg = CDC_RX_RXn_RX_PATH_CTL(rx, interp_idx);
+	dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, interp_idx);
+
 	if (interp_idx == INTERP_AUX)
-		dsm_reg = CDC_RX_RX2_RX_PATH_DSM_CTL;
-	rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(interp_idx);
+		dsm_reg = CDC_RX_RXn_RX_PATH_DSM_CTL(rx, 2);
+
+	rx_cfg2_reg = CDC_RX_RXn_RX_PATH_CFG2(rx, interp_idx);
 
 	if (SND_SOC_DAPM_EVENT_ON(event)) {
 		if (rx->main_clk_users[interp_idx] == 0) {
@@ -2587,10 +2767,11 @@ static int rx_macro_enable_mix_path(struct snd_soc_dapm_widget *w,
 				    struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 	u16 gain_reg, mix_reg;
 
-	gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(w->shift);
-	mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(w->shift);
+	gain_reg = CDC_RX_RXn_RX_VOL_MIX_CTL(rx, w->shift);
+	mix_reg = CDC_RX_RXn_RX_PATH_MIX_CTL(rx, w->shift);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
@@ -2621,17 +2802,18 @@ static int rx_macro_enable_rx_path_clk(struct snd_soc_dapm_widget *w,
 				       struct snd_kcontrol *kcontrol, int event)
 {
 	struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
+	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
 
 	switch (event) {
 	case SND_SOC_DAPM_PRE_PMU:
 		rx_macro_enable_interp_clk(component, event, w->shift);
-		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
+		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
 					      CDC_RX_RXn_SIDETONE_EN_MASK, 1);
-		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(w->shift),
+		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CTL(rx, w->shift),
 					      CDC_RX_PATH_CLK_EN_MASK, 1);
 		break;
 	case SND_SOC_DAPM_POST_PMD:
-		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(w->shift),
+		snd_soc_component_write_field(component, CDC_RX_RXn_RX_PATH_CFG1(rx, w->shift),
 					      CDC_RX_RXn_SIDETONE_EN_MASK, 0);
 		rx_macro_enable_interp_clk(component, event, w->shift);
 		break;
@@ -2801,20 +2983,34 @@ static int rx_macro_iir_filter_info(struct snd_kcontrol *kcontrol,
 	return 0;
 }
 
-static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
-	SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
-			  -84, 40, digital_gain),
+static const struct snd_kcontrol_new rx_macro_def_snd_controls[] = {
 	SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_RX_RX1_RX_VOL_CTL,
 			  -84, 40, digital_gain),
 	SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_RX_RX2_RX_VOL_CTL,
 			  -84, 40, digital_gain),
-	SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
-			  -84, 40, digital_gain),
 	SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_RX_RX1_RX_VOL_MIX_CTL,
 			  -84, 40, digital_gain),
 	SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_RX_RX2_RX_VOL_MIX_CTL,
 			  -84, 40, digital_gain),
+};
+
+static const struct snd_kcontrol_new rx_macro_2_6_snd_controls[] = {
+
+	SOC_SINGLE_S8_TLV("RX_RX1 Digital Volume", CDC_2_6_RX_RX1_RX_VOL_CTL,
+			  -84, 40, digital_gain),
+	SOC_SINGLE_S8_TLV("RX_RX2 Digital Volume", CDC_2_6_RX_RX2_RX_VOL_CTL,
+			  -84, 40, digital_gain),
+	SOC_SINGLE_S8_TLV("RX_RX1 Mix Digital Volume", CDC_2_6_RX_RX1_RX_VOL_MIX_CTL,
+			  -84, 40, digital_gain),
+	SOC_SINGLE_S8_TLV("RX_RX2 Mix Digital Volume", CDC_2_6_RX_RX2_RX_VOL_MIX_CTL,
+			  -84, 40, digital_gain),
+};
 
+static const struct snd_kcontrol_new rx_macro_snd_controls[] = {
+	SOC_SINGLE_S8_TLV("RX_RX0 Digital Volume", CDC_RX_RX0_RX_VOL_CTL,
+			  -84, 40, digital_gain),
+	SOC_SINGLE_S8_TLV("RX_RX0 Mix Digital Volume", CDC_RX_RX0_RX_VOL_MIX_CTL,
+			  -84, 40, digital_gain),
 	SOC_SINGLE_EXT("RX_COMP1 Switch", SND_SOC_NOPM, RX_MACRO_COMP1, 1, 0,
 		rx_macro_get_compander, rx_macro_set_compander),
 	SOC_SINGLE_EXT("RX_COMP2 Switch", SND_SOC_NOPM, RX_MACRO_COMP2, 1, 0,
@@ -2932,6 +3128,16 @@ static int rx_macro_enable_echo(struct snd_soc_dapm_widget *w,
 	return 0;
 }
 
+static const struct snd_soc_dapm_widget rx_macro_2_6_dapm_widgets[] = {
+	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
+			 &rx_2_6_int1_dem_inp_mux),
+};
+
+static const struct snd_soc_dapm_widget rx_macro_def_dapm_widgets[] = {
+	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
+			 &rx_int1_dem_inp_mux),
+};
+
 static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
 	SND_SOC_DAPM_AIF_IN("RX AIF1 PB", "RX_MACRO_AIF1 Playback", 0,
 		SND_SOC_NOPM, 0, 0),
@@ -2948,6 +3154,8 @@ static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
 	SND_SOC_DAPM_AIF_OUT("RX AIF_ECHO", "RX_AIF_ECHO Capture", 0,
 		SND_SOC_NOPM, 0, 0),
 
+	SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
+			 &rx_int0_dem_inp_mux),
 	SND_SOC_DAPM_MUX("RX_MACRO RX0 MUX", SND_SOC_NOPM, RX_MACRO_RX0, 0,
 			 &rx_macro_rx0_mux),
 	SND_SOC_DAPM_MUX("RX_MACRO RX1 MUX", SND_SOC_NOPM, RX_MACRO_RX1, 0,
@@ -3001,10 +3209,6 @@ static const struct snd_soc_dapm_widget rx_macro_dapm_widgets[] = {
 	SND_SOC_DAPM_MIXER("SRC1", CDC_RX_SIDETONE_SRC1_ST_SRC_PATH_CTL,
 		4, 0, NULL, 0),
 
-	SND_SOC_DAPM_MUX("RX INT0 DEM MUX", SND_SOC_NOPM, 0, 0,
-			 &rx_int0_dem_inp_mux),
-	SND_SOC_DAPM_MUX("RX INT1 DEM MUX", SND_SOC_NOPM, 0, 0,
-			 &rx_int1_dem_inp_mux),
 
 	SND_SOC_DAPM_MUX_E("RX INT0_2 MUX", SND_SOC_NOPM, INTERP_HPHL, 0,
 		&rx_int0_2_mux, rx_macro_enable_mix_path,
@@ -3399,32 +3603,53 @@ static const struct snd_soc_dapm_route rx_audio_map[] = {
 
 static int rx_macro_component_probe(struct snd_soc_component *component)
 {
+	struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
 	struct rx_macro *rx = snd_soc_component_get_drvdata(component);
+	const struct snd_soc_dapm_widget *widgets;
+	const struct snd_kcontrol_new *controls;
+	unsigned int num_controls;
+	int ret, num_widgets;
 
 	snd_soc_component_init_regmap(component, rx->regmap);
 
-	snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_SEC7,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 0),
 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
-	snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_SEC7,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 1),
 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
-	snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_SEC7,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_SEC7(rx, 2),
 				      CDC_RX_DSM_OUT_DELAY_SEL_MASK,
 				      CDC_RX_DSM_OUT_DELAY_TWO_SAMPLE);
-	snd_soc_component_update_bits(component, CDC_RX_RX0_RX_PATH_CFG3,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 0),
 				      CDC_RX_DC_COEFF_SEL_MASK,
 				      CDC_RX_DC_COEFF_SEL_TWO);
-	snd_soc_component_update_bits(component, CDC_RX_RX1_RX_PATH_CFG3,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 1),
 				      CDC_RX_DC_COEFF_SEL_MASK,
 				      CDC_RX_DC_COEFF_SEL_TWO);
-	snd_soc_component_update_bits(component, CDC_RX_RX2_RX_PATH_CFG3,
+	snd_soc_component_update_bits(component, CDC_RX_RXn_RX_PATH_CFG3(rx, 2),
 				      CDC_RX_DC_COEFF_SEL_MASK,
 				      CDC_RX_DC_COEFF_SEL_TWO);
 
+	if (rx->codec_version == LPASS_CODEC_VERSION_2_6) {
+		controls = rx_macro_2_6_snd_controls;
+		num_controls = ARRAY_SIZE(rx_macro_2_6_snd_controls);
+		widgets = rx_macro_2_6_dapm_widgets;
+		num_widgets = ARRAY_SIZE(rx_macro_2_6_dapm_widgets);
+	} else {
+		controls = rx_macro_def_snd_controls;
+		num_controls = ARRAY_SIZE(rx_macro_def_snd_controls);
+		widgets = rx_macro_def_dapm_widgets;
+		num_widgets = ARRAY_SIZE(rx_macro_def_dapm_widgets);
+	}
+
 	rx->component = component;
 
-	return 0;
+	ret = snd_soc_add_component_controls(component, controls, num_controls);
+	if (ret)
+		return ret;
+
+	return snd_soc_dapm_new_controls(dapm, widgets, num_widgets);
 }
 
 static int swclk_gate_enable(struct clk_hw *hw)
@@ -3523,11 +3748,12 @@ static const struct snd_soc_component_driver rx_macro_component_drv = {
 
 static int rx_macro_probe(struct platform_device *pdev)
 {
+	struct reg_default *reg_defaults;
 	struct device *dev = &pdev->dev;
 	kernel_ulong_t flags;
 	struct rx_macro *rx;
 	void __iomem *base;
-	int ret;
+	int ret, def_count;
 
 	flags = (kernel_ulong_t)device_get_match_data(dev);
 
@@ -3567,6 +3793,33 @@ static int rx_macro_probe(struct platform_device *pdev)
 		goto err;
 	}
 
+	rx->codec_version = lpass_macro_get_codec_version();
+	switch (rx->codec_version) {
+	case LPASS_CODEC_VERSION_2_6:
+		rx->rxn_reg_offset = 0xc0;
+		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_6_defaults);
+		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
+		if (!reg_defaults)
+			return -ENOMEM;
+		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
+		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
+				rx_2_6_defaults, sizeof(rx_2_6_defaults));
+		break;
+	default:
+		rx->rxn_reg_offset = 0x80;
+		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_6_defaults);
+		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
+		if (!reg_defaults)
+			return -ENOMEM;
+		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
+		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
+				rx_pre_2_6_defaults, sizeof(rx_pre_2_6_defaults));
+		break;
+	}
+
+	rx_regmap_config.reg_defaults = reg_defaults,
+	rx_regmap_config.num_reg_defaults = def_count;
+
 	rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
 	if (IS_ERR(rx->regmap)) {
 		ret = PTR_ERR(rx->regmap);
@@ -3629,6 +3882,7 @@ static int rx_macro_probe(struct platform_device *pdev)
 	if (ret)
 		goto err_clkout;
 
+	kfree(reg_defaults);
 	return 0;
 
 err_clkout:
@@ -3642,6 +3896,7 @@ static int rx_macro_probe(struct platform_device *pdev)
 err_dcodec:
 	clk_disable_unprepare(rx->macro);
 err:
+	kfree(reg_defaults);
 	lpass_macro_pds_exit(rx->pds);
 
 	return ret;
-- 
2.25.1


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version
  2024-05-10 17:58 ` [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 " srinivas.kandagatla
@ 2024-05-15 14:30   ` Dan Carpenter
  0 siblings, 0 replies; 6+ messages in thread
From: Dan Carpenter @ 2024-05-15 14:30 UTC (permalink / raw)
  To: oe-kbuild, srinivas.kandagatla, broonie
  Cc: lkp, oe-kbuild-all, perex, tiwai, alsa-devel, lgirdwood,
	linux-kernel, krzysztof.kozlowski, neil.armstrong,
	Srinivas Kandagatla

Hi,

kernel test robot noticed the following build warnings:

https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/srinivas-kandagatla-linaro-org/ASoC-codecs-lpass-macro-add-helpers-to-get-codec-version/20240511-020042
base:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
patch link:    https://lore.kernel.org/r/20240510175835.286775-3-srinivas.kandagatla%40linaro.org
patch subject: [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version
config: sparc-randconfig-r081-20240512 (https://download.01.org/0day-ci/archive/20240512/202405120902.nPmp732h-lkp@intel.com/config)
compiler: sparc64-linux-gcc (GCC) 13.2.0

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202405120902.nPmp732h-lkp@intel.com/

New smatch warnings:
sound/soc/codecs/lpass-rx-macro.c:3899 rx_macro_probe() error: uninitialized symbol 'reg_defaults'.
sound/soc/codecs/lpass-rx-macro.c:3813 rx_macro_probe() warn: missing unwind goto?

vim +/reg_defaults +3899 sound/soc/codecs/lpass-rx-macro.c

af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3749  static int rx_macro_probe(struct platform_device *pdev)
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3750  {
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3751  	struct reg_default *reg_defaults;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3752  	struct device *dev = &pdev->dev;
492fe974fed075 Krzysztof Kozlowski     2023-03-13  3753  	kernel_ulong_t flags;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3754  	struct rx_macro *rx;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3755  	void __iomem *base;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3756  	int ret, def_count;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3757  
492fe974fed075 Krzysztof Kozlowski     2023-03-13  3758  	flags = (kernel_ulong_t)device_get_match_data(dev);
492fe974fed075 Krzysztof Kozlowski     2023-03-13  3759  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3760  	rx = devm_kzalloc(dev, sizeof(*rx), GFP_KERNEL);
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3761  	if (!rx)
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3762  		return -ENOMEM;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3763  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3764  	rx->macro = devm_clk_get_optional(dev, "macro");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3765  	if (IS_ERR(rx->macro))
f54e3474507427 Bjorn Andersson         2023-07-21  3766  		return dev_err_probe(dev, PTR_ERR(rx->macro), "unable to get macro clock\n");
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3767  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3768  	rx->dcodec = devm_clk_get_optional(dev, "dcodec");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3769  	if (IS_ERR(rx->dcodec))
f54e3474507427 Bjorn Andersson         2023-07-21  3770  		return dev_err_probe(dev, PTR_ERR(rx->dcodec), "unable to get dcodec clock\n");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3771  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3772  	rx->mclk = devm_clk_get(dev, "mclk");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3773  	if (IS_ERR(rx->mclk))
f54e3474507427 Bjorn Andersson         2023-07-21  3774  		return dev_err_probe(dev, PTR_ERR(rx->mclk), "unable to get mclk clock\n");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3775  
492fe974fed075 Krzysztof Kozlowski     2023-03-13  3776  	if (flags & LPASS_MACRO_FLAG_HAS_NPL_CLOCK) {
43b647d9940454 Srinivas Kandagatla     2022-02-24  3777  		rx->npl = devm_clk_get(dev, "npl");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3778  		if (IS_ERR(rx->npl))
f54e3474507427 Bjorn Andersson         2023-07-21  3779  			return dev_err_probe(dev, PTR_ERR(rx->npl), "unable to get npl clock\n");
492fe974fed075 Krzysztof Kozlowski     2023-03-13  3780  	}
43b647d9940454 Srinivas Kandagatla     2022-02-24  3781  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3782  	rx->fsgen = devm_clk_get(dev, "fsgen");
43b647d9940454 Srinivas Kandagatla     2022-02-24  3783  	if (IS_ERR(rx->fsgen))
f54e3474507427 Bjorn Andersson         2023-07-21  3784  		return dev_err_probe(dev, PTR_ERR(rx->fsgen), "unable to get fsgen clock\n");
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3785  
9e3d83c52844f9 Srinivasa Rao Mandadapu 2022-02-26  3786  	rx->pds = lpass_macro_pds_init(dev);
9e3d83c52844f9 Srinivasa Rao Mandadapu 2022-02-26  3787  	if (IS_ERR(rx->pds))
9e3d83c52844f9 Srinivasa Rao Mandadapu 2022-02-26  3788  		return PTR_ERR(rx->pds);
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3789  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3790  	base = devm_platform_ioremap_resource(pdev, 0);
ddfd5345281466 Christophe JAILLET      2022-04-03  3791  	if (IS_ERR(base)) {
ddfd5345281466 Christophe JAILLET      2022-04-03  3792  		ret = PTR_ERR(base);
ddfd5345281466 Christophe JAILLET      2022-04-03  3793  		goto err;

reg_defaults is uninitialized here.

ddfd5345281466 Christophe JAILLET      2022-04-03  3794  	}
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3795  
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3796  	rx->codec_version = lpass_macro_get_codec_version();
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3797  	switch (rx->codec_version) {
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3798  	case LPASS_CODEC_VERSION_2_6:
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3799  		rx->rxn_reg_offset = 0xc0;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3800  		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_2_6_defaults);
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3801  		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3802  		if (!reg_defaults)
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3803  			return -ENOMEM;

need to call lpass_macro_pds_exit(rx->pds) before returning.

0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3804  		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3805  		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3806  				rx_2_6_defaults, sizeof(rx_2_6_defaults));
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3807  		break;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3808  	default:
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3809  		rx->rxn_reg_offset = 0x80;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3810  		def_count = ARRAY_SIZE(rx_defaults) + ARRAY_SIZE(rx_pre_2_6_defaults);
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3811  		reg_defaults = kmalloc_array(def_count, sizeof(struct reg_default), GFP_KERNEL);
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3812  		if (!reg_defaults)
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10 @3813  			return -ENOMEM;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3814  		memcpy(&reg_defaults[0], rx_defaults, sizeof(rx_defaults));
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3815  		memcpy(&reg_defaults[ARRAY_SIZE(rx_defaults)],
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3816  				rx_pre_2_6_defaults, sizeof(rx_pre_2_6_defaults));
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3817  		break;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3818  	}
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3819  
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3820  	rx_regmap_config.reg_defaults = reg_defaults,
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3821  	rx_regmap_config.num_reg_defaults = def_count;
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3822  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3823  	rx->regmap = devm_regmap_init_mmio(dev, base, &rx_regmap_config);
ddfd5345281466 Christophe JAILLET      2022-04-03  3824  	if (IS_ERR(rx->regmap)) {
ddfd5345281466 Christophe JAILLET      2022-04-03  3825  		ret = PTR_ERR(rx->regmap);
ddfd5345281466 Christophe JAILLET      2022-04-03  3826  		goto err;
ddfd5345281466 Christophe JAILLET      2022-04-03  3827  	}
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3828  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3829  	dev_set_drvdata(dev, rx);
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3830  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3831  	rx->dev = dev;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3832  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3833  	/* set MCLK and NPL rates */
43b647d9940454 Srinivas Kandagatla     2022-02-24  3834  	clk_set_rate(rx->mclk, MCLK_FREQ);
e7621434378c40 Srinivas Kandagatla     2023-02-09  3835  	clk_set_rate(rx->npl, MCLK_FREQ);
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3836  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3837  	ret = clk_prepare_enable(rx->macro);
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3838  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3839  		goto err;
43b647d9940454 Srinivas Kandagatla     2022-02-24  3840  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3841  	ret = clk_prepare_enable(rx->dcodec);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3842  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3843  		goto err_dcodec;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3844  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3845  	ret = clk_prepare_enable(rx->mclk);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3846  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3847  		goto err_mclk;
43b647d9940454 Srinivas Kandagatla     2022-02-24  3848  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3849  	ret = clk_prepare_enable(rx->npl);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3850  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3851  		goto err_npl;
43b647d9940454 Srinivas Kandagatla     2022-02-24  3852  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3853  	ret = clk_prepare_enable(rx->fsgen);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3854  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3855  		goto err_fsgen;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3856  
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3857  	/* reset swr block  */
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3858  	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3859  			   CDC_RX_SWR_RESET_MASK,
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3860  			   CDC_RX_SWR_RESET);
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3861  
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3862  	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3863  			   CDC_RX_SWR_CLK_EN_MASK, 1);
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3864  
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3865  	regmap_update_bits(rx->regmap, CDC_RX_CLK_RST_CTRL_SWR_CONTROL,
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3866  			   CDC_RX_SWR_RESET_MASK, 0);
ddffe3b82849ba Srinivas Kandagatla     2023-02-09  3867  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3868  	ret = devm_snd_soc_register_component(dev, &rx_macro_component_drv,
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3869  					      rx_macro_dai,
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3870  					      ARRAY_SIZE(rx_macro_dai));
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3871  	if (ret)
43b647d9940454 Srinivas Kandagatla     2022-02-24  3872  		goto err_clkout;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3873  
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3874  
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3875  	pm_runtime_set_autosuspend_delay(dev, 3000);
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3876  	pm_runtime_use_autosuspend(dev);
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3877  	pm_runtime_mark_last_busy(dev);
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3878  	pm_runtime_set_active(dev);
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3879  	pm_runtime_enable(dev);
366ff79ed5392a Srinivas Kandagatla     2022-02-24  3880  
1dc3459009c33e Srinivas Kandagatla     2023-02-09  3881  	ret = rx_macro_register_mclk_output(rx);
1dc3459009c33e Srinivas Kandagatla     2023-02-09  3882  	if (ret)
1dc3459009c33e Srinivas Kandagatla     2023-02-09  3883  		goto err_clkout;
1dc3459009c33e Srinivas Kandagatla     2023-02-09  3884  
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10  3885  	kfree(reg_defaults);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3886  	return 0;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3887  
43b647d9940454 Srinivas Kandagatla     2022-02-24  3888  err_clkout:
43b647d9940454 Srinivas Kandagatla     2022-02-24  3889  	clk_disable_unprepare(rx->fsgen);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3890  err_fsgen:
43b647d9940454 Srinivas Kandagatla     2022-02-24  3891  	clk_disable_unprepare(rx->npl);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3892  err_npl:
43b647d9940454 Srinivas Kandagatla     2022-02-24  3893  	clk_disable_unprepare(rx->mclk);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3894  err_mclk:
43b647d9940454 Srinivas Kandagatla     2022-02-24  3895  	clk_disable_unprepare(rx->dcodec);
43b647d9940454 Srinivas Kandagatla     2022-02-24  3896  err_dcodec:
43b647d9940454 Srinivas Kandagatla     2022-02-24  3897  	clk_disable_unprepare(rx->macro);
70a5e96bad5921 Srinivas Kandagatla     2022-02-24  3898  err:
0e15d4b2b2519d Srinivas Kandagatla     2024-05-10 @3899  	kfree(reg_defaults);
ddfd5345281466 Christophe JAILLET      2022-04-03  3900  	lpass_macro_pds_exit(rx->pds);
ddfd5345281466 Christophe JAILLET      2022-04-03  3901  
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3902  	return ret;
af3d54b99764f0 Srinivas Kandagatla     2021-02-11  3903  }

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki


^ permalink raw reply	[flat|nested] 6+ messages in thread

* Re: [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro
  2024-05-10 17:58 [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro srinivas.kandagatla
  2024-05-10 17:58 ` [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version srinivas.kandagatla
  2024-05-10 17:58 ` [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 " srinivas.kandagatla
@ 2024-06-17 17:26 ` Mark Brown
  2 siblings, 0 replies; 6+ messages in thread
From: Mark Brown @ 2024-06-17 17:26 UTC (permalink / raw)
  To: srinivas.kandagatla
  Cc: perex, tiwai, alsa-devel, lgirdwood, linux-kernel,
	krzysztof.kozlowski, neil.armstrong

On Fri, 10 May 2024 18:58:33 +0100, srinivas.kandagatla@linaro.org wrote:
> This patchset adds support to reading codec version and also adds
> support for v2.6 codec version in rx macro.
> 
> LPASS 2.6 has changes in some of the rx block which are required to get
> headset functional correctly.
> 
> Tested this on X13s and x1e80100 crd.
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next

Thanks!

[1/2] ASoC: codecs: lpass-macro: add helpers to get codec version
      commit: 378918d5918116b95300dd7f03913a1d0841f223
[2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 codec version
      (no commit info)

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply	[flat|nested] 6+ messages in thread

end of thread, other threads:[~2024-06-17 17:26 UTC | newest]

Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2024-05-10 17:58 [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro srinivas.kandagatla
2024-05-10 17:58 ` [PATCH 1/2] ASoC: codecs: lpass-macro: add helpers to get codec version srinivas.kandagatla
2024-05-15 14:28   ` Dan Carpenter
2024-05-10 17:58 ` [PATCH 2/2] ASoC: codec: lpass-rx-macro: add suppor for 2.6 " srinivas.kandagatla
2024-05-15 14:30   ` Dan Carpenter
2024-06-17 17:26 ` [PATCH 0/2] ASoC: codecs: lpass: add support for v2.6 rx macro Mark Brown

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