[tip: irq/core] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

[tip: irq/core] irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

[tip-bot2 for Marek Behún]

The following commit has been merged into the irq/core branch of tip:

Commit-ID:     d6ca3f440239fb4fa85228ead4c5e8b286645b7e
Gitweb:        https://git.kernel.org/tip/d6ca3f440239fb4fa85228ead4c5e8b286645b7e
Author:        Marek Behún <kabel@kernel.org>
AuthorDate:    Wed, 07 Aug 2024 18:41:03 +02:00
Committer:     Thomas Gleixner <tglx@linutronix.de>
CommitterDate: Thu, 08 Aug 2024 17:15:01 +02:00

irqchip/armada-370-xp: Allow mapping only per-CPU interrupts

On platforms where MPIC is not the top-level interrupt controller the
driver currently only supports handling of the per-CPU interrupts (the
first 29 interrupts). This is obvious from the code of
mpic_handle_cascade_irq(), which reads only one cause register.

Bound the number of available interrupts in the interrupt domain to 29 for
these platforms.

The corresponding device-trees refer only to per-CPU interrupts via MPIC,
the other interrupts are referred to via GIC.

Signed-off-by: Marek Behún <kabel@kernel.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

---
 drivers/irqchip/irq-armada-370-xp.c | 19 +++++++++++++------
 1 file changed, 13 insertions(+), 6 deletions(-)

diff --git a/drivers/irqchip/irq-armada-370-xp.c b/drivers/irqchip/irq-armada-370-xp.c
index 36d1bac..4f3f99a 100644
--- a/drivers/irqchip/irq-armada-370-xp.c
+++ b/drivers/irqchip/irq-armada-370-xp.c
@@ -848,6 +848,19 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par
 	for (irq_hw_number_t i = 0; i < nr_irqs; i++)
 		writel(i, mpic->base + MPIC_INT_CLEAR_ENABLE);
 
+	/*
+	 * Initialize mpic->parent_irq before calling any other functions, since
+	 * it is used to distinguish between IPI and non-IPI platforms.
+	 */
+	mpic->parent_irq = irq_of_parse_and_map(node, 0);
+
+	/*
+	 * On non-IPI platforms the driver currently supports only the per-CPU
+	 * interrupts (the first 29 interrupts). See mpic_handle_cascade_irq().
+	 */
+	if (!mpic_is_ipi_available(mpic))
+		nr_irqs = MPIC_PER_CPU_IRQS_NR;
+
 	mpic->domain = irq_domain_add_linear(node, nr_irqs, &mpic_irq_ops, mpic);
 	if (!mpic->domain) {
 		pr_err("%pOF: Unable to add IRQ domain\n", node);
@@ -856,12 +869,6 @@ static int __init mpic_of_init(struct device_node *node, struct device_node *par
 
 	irq_domain_update_bus_token(mpic->domain, DOMAIN_BUS_WIRED);
 
-	/*
-	 * Initialize mpic->parent_irq before calling any other functions, since
-	 * it is used to distinguish between IPI and non-IPI platforms.
-	 */
-	mpic->parent_irq = irq_of_parse_and_map(node, 0);
-
 	/* Setup for the boot CPU */
 	mpic_perf_init(mpic);
 	mpic_smp_cpu_init(mpic);