* [PATCH net-next v3 1/2] dt-bindings: net: dp83822: Add support for GPIO2 clock output
2024-12-12 8:44 [PATCH net-next v3 0/2] net: phy: dp83822: Add support for GPIO2 clock output Dimitri Fedrau via B4 Relay
@ 2024-12-12 8:44 ` Dimitri Fedrau via B4 Relay
2024-12-13 9:10 ` Krzysztof Kozlowski
2024-12-13 10:07 ` Andrew Lunn
2024-12-12 8:44 ` [PATCH net-next v3 2/2] net: phy: " Dimitri Fedrau via B4 Relay
2024-12-15 21:20 ` [PATCH net-next v3 0/2] " patchwork-bot+netdevbpf
2 siblings, 2 replies; 7+ messages in thread
From: Dimitri Fedrau via B4 Relay @ 2024-12-12 8:44 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andrew Davis, Andrew Lunn, Heiner Kallweit, Russell King
Cc: netdev, devicetree, linux-kernel, Dimitri Fedrau, Dimitri Fedrau
From: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
The GPIO2 pin on the DP83822 can be configured as clock output. Add
binding to support this feature.
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
---
.../devicetree/bindings/net/ti,dp83822.yaml | 27 ++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/Documentation/devicetree/bindings/net/ti,dp83822.yaml b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
index 784866ea392b2083e93d8dc9aaea93b70dc80934..50c24248df266f1950371b950cd9c4d417835f97 100644
--- a/Documentation/devicetree/bindings/net/ti,dp83822.yaml
+++ b/Documentation/devicetree/bindings/net/ti,dp83822.yaml
@@ -96,6 +96,32 @@ properties:
- master
- slave
+ ti,gpio2-clk-out:
+ description: |
+ DP83822 PHY only.
+ The GPIO2 pin on the DP83822 can be configured as clock output. When
+ omitted, the PHY's default will be left as is.
+
+ - 'mac-if': In MII mode the clock frequency is 25-MHz, in RMII Mode the
+ clock frequency is 50-MHz and in RGMII Mode the clock frequency is
+ 25-MHz.
+ - 'xi': XI clock(pass-through clock from XI pin).
+ - 'int-ref': Internal reference clock 25-MHz.
+ - 'rmii-master-mode-ref': RMII master mode reference clock 50-MHz. RMII
+ master mode reference clock is identical to MAC IF clock in RMII master
+ mode.
+ - 'free-running': Free running clock 125-MHz.
+ - 'recovered': Recovered clock is a 125-MHz recovered clock from a
+ connected link partner.
+ $ref: /schemas/types.yaml#/definitions/string
+ enum:
+ - mac-if
+ - xi
+ - int-ref
+ - rmii-master-mode-ref
+ - free-running
+ - recovered
+
required:
- reg
@@ -110,6 +136,7 @@ examples:
reg = <0>;
rx-internal-delay-ps = <1>;
tx-internal-delay-ps = <1>;
+ ti,gpio2-clk-out = "xi";
};
};
--
2.39.5
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH net-next v3 2/2] net: phy: dp83822: Add support for GPIO2 clock output
2024-12-12 8:44 [PATCH net-next v3 0/2] net: phy: dp83822: Add support for GPIO2 clock output Dimitri Fedrau via B4 Relay
2024-12-12 8:44 ` [PATCH net-next v3 1/2] dt-bindings: net: " Dimitri Fedrau via B4 Relay
@ 2024-12-12 8:44 ` Dimitri Fedrau via B4 Relay
2024-12-13 10:08 ` Andrew Lunn
2024-12-15 21:20 ` [PATCH net-next v3 0/2] " patchwork-bot+netdevbpf
2 siblings, 1 reply; 7+ messages in thread
From: Dimitri Fedrau via B4 Relay @ 2024-12-12 8:44 UTC (permalink / raw)
To: Andrew Lunn, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Andrew Davis, Andrew Lunn, Heiner Kallweit, Russell King
Cc: netdev, devicetree, linux-kernel, Dimitri Fedrau, Dimitri Fedrau
From: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
The GPIO2 pin on the DP83822 can be configured as clock output. Add support
for configuration via DT.
Signed-off-by: Dimitri Fedrau <dimitri.fedrau@liebherr.com>
---
drivers/net/phy/dp83822.c | 48 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 48 insertions(+)
diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c
index 25ee09c48027c86b7d8f4acb5cbe2e157c56a85a..334c17a68edd7c2a0f707b3ccafaa7a870818fbe 100644
--- a/drivers/net/phy/dp83822.c
+++ b/drivers/net/phy/dp83822.c
@@ -30,6 +30,7 @@
#define MII_DP83822_FCSCR 0x14
#define MII_DP83822_RCSR 0x17
#define MII_DP83822_RESET_CTRL 0x1f
+#define MII_DP83822_IOCTRL2 0x463
#define MII_DP83822_GENCFG 0x465
#define MII_DP83822_SOR1 0x467
@@ -104,6 +105,18 @@
#define DP83822_RX_CLK_SHIFT BIT(12)
#define DP83822_TX_CLK_SHIFT BIT(11)
+/* IOCTRL2 bits */
+#define DP83822_IOCTRL2_GPIO2_CLK_SRC GENMASK(6, 4)
+#define DP83822_IOCTRL2_GPIO2_CTRL GENMASK(2, 0)
+#define DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF GENMASK(1, 0)
+
+#define DP83822_CLK_SRC_MAC_IF 0x0
+#define DP83822_CLK_SRC_XI 0x1
+#define DP83822_CLK_SRC_INT_REF 0x2
+#define DP83822_CLK_SRC_RMII_MASTER_MODE_REF 0x4
+#define DP83822_CLK_SRC_FREE_RUNNING 0x6
+#define DP83822_CLK_SRC_RECOVERED 0x7
+
/* SOR1 mode */
#define DP83822_STRAP_MODE1 0
#define DP83822_STRAP_MODE2 BIT(0)
@@ -139,6 +152,8 @@ struct dp83822_private {
u8 cfg_dac_minus;
u8 cfg_dac_plus;
struct ethtool_wolinfo wol;
+ bool set_gpio2_clk_out;
+ u32 gpio2_clk_out;
};
static int dp83822_config_wol(struct phy_device *phydev,
@@ -413,6 +428,15 @@ static int dp83822_config_init(struct phy_device *phydev)
int err = 0;
int bmcr;
+ if (dp83822->set_gpio2_clk_out)
+ phy_modify_mmd(phydev, MDIO_MMD_VEND2, MII_DP83822_IOCTRL2,
+ DP83822_IOCTRL2_GPIO2_CTRL |
+ DP83822_IOCTRL2_GPIO2_CLK_SRC,
+ FIELD_PREP(DP83822_IOCTRL2_GPIO2_CTRL,
+ DP83822_IOCTRL2_GPIO2_CTRL_CLK_REF) |
+ FIELD_PREP(DP83822_IOCTRL2_GPIO2_CLK_SRC,
+ dp83822->gpio2_clk_out));
+
if (phy_interface_is_rgmii(phydev)) {
rx_int_delay = phy_get_internal_delay(phydev, dev, NULL, 0,
true);
@@ -611,6 +635,7 @@ static int dp83822_of_init(struct phy_device *phydev)
{
struct dp83822_private *dp83822 = phydev->priv;
struct device *dev = &phydev->mdio.dev;
+ const char *of_val;
/* Signal detection for the PHY is only enabled if the FX_EN and the
* SD_EN pins are strapped. Signal detection can only enabled if FX_EN
@@ -623,6 +648,29 @@ static int dp83822_of_init(struct phy_device *phydev)
dp83822->fx_enabled = device_property_present(dev,
"ti,fiber-mode");
+ if (!device_property_read_string(dev, "ti,gpio2-clk-out", &of_val)) {
+ if (strcmp(of_val, "mac-if") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_MAC_IF;
+ } else if (strcmp(of_val, "xi") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_XI;
+ } else if (strcmp(of_val, "int-ref") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_INT_REF;
+ } else if (strcmp(of_val, "rmii-master-mode-ref") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_RMII_MASTER_MODE_REF;
+ } else if (strcmp(of_val, "free-running") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_FREE_RUNNING;
+ } else if (strcmp(of_val, "recovered") == 0) {
+ dp83822->gpio2_clk_out = DP83822_CLK_SRC_RECOVERED;
+ } else {
+ phydev_err(phydev,
+ "Invalid value for ti,gpio2-clk-out property (%s)\n",
+ of_val);
+ return -EINVAL;
+ }
+
+ dp83822->set_gpio2_clk_out = true;
+ }
+
return 0;
}
--
2.39.5
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH net-next v3 0/2] net: phy: dp83822: Add support for GPIO2 clock output
2024-12-12 8:44 [PATCH net-next v3 0/2] net: phy: dp83822: Add support for GPIO2 clock output Dimitri Fedrau via B4 Relay
2024-12-12 8:44 ` [PATCH net-next v3 1/2] dt-bindings: net: " Dimitri Fedrau via B4 Relay
2024-12-12 8:44 ` [PATCH net-next v3 2/2] net: phy: " Dimitri Fedrau via B4 Relay
@ 2024-12-15 21:20 ` patchwork-bot+netdevbpf
2 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+netdevbpf @ 2024-12-15 21:20 UTC (permalink / raw)
To: Dimitri Fedrau via B4 Relay
Cc: andrew+netdev, davem, edumazet, kuba, pabeni, robh, krzk+dt,
conor+dt, afd, andrew, hkallweit1, linux, netdev, devicetree,
linux-kernel, dimitri.fedrau, dima.fedrau
Hello:
This series was applied to netdev/net-next.git (main)
by David S. Miller <davem@davemloft.net>:
On Thu, 12 Dec 2024 09:44:05 +0100 you wrote:
> The DP83822 has several clock configuration options for pins GPIO1, GPIO2
> and GPIO3. Clock options include:
> - MAC IF clock
> - XI clock
> - Free-Running clock
> - Recovered clock
> This patch adds support for GPIO2, the support for GPIO1 and GPIO3 can be
> easily added if needed. Code and device tree bindings are derived from
> dp83867 which has a similar feature.
>
> [...]
Here is the summary with links:
- [net-next,v3,1/2] dt-bindings: net: dp83822: Add support for GPIO2 clock output
https://git.kernel.org/netdev/net-next/c/a2d8af57452e
- [net-next,v3,2/2] net: phy: dp83822: Add support for GPIO2 clock output
https://git.kernel.org/netdev/net-next/c/53e3b540952c
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread