[PATCH v4 0/9] Add support to configure CPG block for watchdog on RZ/V2H(P) and RZ/G3E SoCs

[PATCH v4 0/9] Add support to configure CPG block for watchdog on RZ/V2H(P) and RZ/G3E SoCs

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Hi All,

This patch series adds SYSCON support to configure and retrieve boot
status information from the CPG block for the RZ/V2H(P) and RZ/G3E SoCs.
Summary of Changes,

    Clock:
        Add syscon compatible support to the CPG block in bindings and
        device trees.

    Watchdog:
        Document the renesas,r9a09g057-syscon-wdt-errorrst property.
        Update the watchdog driver to fetch and report boot status via
        Error Reset Registers (CPG_ERROR_RSTm) and configure the
        CPG_ERRORRST_SEL2 register.

    Device Tree:
        -Add the syscon property to CPG nodes in R9A09G057 and R9A09G047
         SoC DTSI.
        -Add the renesas,syscon-cpg-error-rst property to WDT nodes in
         R9A09G057 and R9A09G047 SoC DTSI.

v3->v4
- Added support to configure CPG_ERRORRST_SEL2 register
- Updated commit messages

v2->v3
- Updated comment section to mention there aren't any ABI breakages with
  this patch series.

Cheers,
Prabhakar

Lad Prabhakar (9):
  dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG
  clk: renesas: Kconfig: Select MFD_SYSCON for RZ/V2H(P) family driver
  arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node
  arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node
  dt-bindings: watchdog: renesas: Document
    `renesas,syscon-cpg-error-rst` property
  watchdog: rzv2h_wdt: Add support to retrieve the bootstatus
    information
  watchdog: rzv2h_wdt: Configure CPG_ERRORRST_SEL2 register
  arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst`
    property to WDT node
  arm64: dts: renesas: r9a09g047: Add `renesas,syscon-cpg-error-rst`
    property to WDT node

 .../bindings/clock/renesas,rzv2h-cpg.yaml     | 10 ++--
 .../bindings/watchdog/renesas,wdt.yaml        | 17 ++++++
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi    |  5 +-
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi    |  6 ++-
 drivers/clk/renesas/Kconfig                   |  1 +
 drivers/watchdog/rzv2h_wdt.c                  | 54 +++++++++++++++++++
 6 files changed, 87 insertions(+), 6 deletions(-)

-- 
2.43.0

[PATCH v4 1/9] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
(`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
trigger a system reset in response to specific error conditions, while the
`CPG_ERROR_RSTm` registers store the error interrupt factors that caused
the system reset. These registers can be used by various IP blocks as
needed.

For example, in `CPG_ERRORRST_SEL2`, setting `BIT(1)` enables the WDT1 to
issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)`
in `CPG_ERROR_RST2` indicates whether the system reset was caused by a
WDT1 underflow. This functionality allows the watchdog driver to configure
the CPG_ERRORRST_SEL2 register and determine whether the system booted due
to a `Power-on Reset` or a `Watchdog Reset`.

Add the `syscon` compatible property to the RZ/V2H(P) and RZ/G3E CPG
blocks, enabling drivers to access the `CPG_ERRORRST_SELm` and
`CPG_ERROR_RSTm` registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- Updated commit meessage

v2->v3
- No change

v1->v2
- No change
---
 .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
index c3fe76abd549..f42d79e73e70 100644
--- a/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
+++ b/Documentation/devicetree/bindings/clock/renesas,rzv2h-cpg.yaml
@@ -17,9 +17,11 @@ description:
 
 properties:
   compatible:
-    enum:
-      - renesas,r9a09g047-cpg # RZ/G3E
-      - renesas,r9a09g057-cpg # RZ/V2H
+    items:
+      - enum:
+          - renesas,r9a09g047-cpg # RZ/G3E
+          - renesas,r9a09g057-cpg # RZ/V2H
+      - const: syscon
 
   reg:
     maxItems: 1
@@ -73,7 +75,7 @@ additionalProperties: false
 examples:
   - |
     clock-controller@10420000 {
-        compatible = "renesas,r9a09g057-cpg";
+        compatible = "renesas,r9a09g057-cpg", "syscon";
         reg = <0x10420000 0x10000>;
         clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
         clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

Re: [PATCH v4 1/9] dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 18:49:02 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
> Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
> (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
> trigger a system reset in response to specific error conditions, while the
> `CPG_ERROR_RSTm` registers store the error interrupt factors that caused
> the system reset. These registers can be used by various IP blocks as
> needed.
> 
> For example, in `CPG_ERRORRST_SEL2`, setting `BIT(1)` enables the WDT1 to
> issue a system reset upon a watchdog timer underflow. Similarly, `BIT(1)`
> in `CPG_ERROR_RST2` indicates whether the system reset was caused by a
> WDT1 underflow. This functionality allows the watchdog driver to configure
> the CPG_ERRORRST_SEL2 register and determine whether the system booted due
> to a `Power-on Reset` or a `Watchdog Reset`.
> 
> Add the `syscon` compatible property to the RZ/V2H(P) and RZ/G3E CPG
> blocks, enabling drivers to access the `CPG_ERRORRST_SELm` and
> `CPG_ERROR_RSTm` registers as needed.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v3->v4
> - Updated commit meessage
> 
> v2->v3
> - No change
> 
> v1->v2
> - No change
> ---
>  .../devicetree/bindings/clock/renesas,rzv2h-cpg.yaml   | 10 ++++++----
>  1 file changed, 6 insertions(+), 4 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v4 2/9] clk: renesas: Kconfig: Select MFD_SYSCON for RZ/V2H(P) family driver

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Explicitly select `MFD_SYSCON` for RZ/V2H(P) family driver.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- New patch
---
 drivers/clk/renesas/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 5a4bc3f94d49..617e824004b1 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -240,6 +240,7 @@ config CLK_RZG2L
 
 config CLK_RZV2H
 	bool "RZ/{G3E,V2H(P)} family clock support" if COMPILE_TEST
+	select MFD_SYSCON
 	select RESET_CONTROLLER
 
 config CLK_RENESAS_VBATTB
-- 
2.43.0

[PATCH v4 3/9] arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `syscon` compatible for CPG node to allow the IP blocks to interact
with the CPG registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- No change

v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index c93aa16d0a6e..c366bd2667ff 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -145,7 +145,7 @@ pinctrl: pinctrl@10410000 {
 		};
 
 		cpg: clock-controller@10420000 {
-			compatible = "renesas,r9a09g047-cpg";
+			compatible = "renesas,r9a09g047-cpg", "syscon";
 			reg = <0 0x10420000 0 0x10000>;
 			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
 			clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

[PATCH v4 4/9] arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `syscon` compatible for CPG node to allow the IP blocks to interact
with the CPG registers as needed.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- No change

v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 0cd00bb05191..acc9c512fbab 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -264,7 +264,7 @@ pinctrl: pinctrl@10410000 {
 		};
 
 		cpg: clock-controller@10420000 {
-			compatible = "renesas,r9a09g057-cpg";
+			compatible = "renesas,r9a09g057-cpg", "syscon";
 			reg = <0 0x10420000 0 0x10000>;
 			clocks = <&audio_extal_clk>, <&rtxin_clk>, <&qextal_clk>;
 			clock-names = "audio_extal", "rtxin", "qextal";
-- 
2.43.0

[PATCH v4 5/9] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
(`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
trigger a system reset in response to specific error conditions, while the
`CPG_ERROR_RSTm` registers store the error interrupt factors that caused
the system reset.

For the watchdog IP to trigger a system reset on a watchdog timer
underflow, the `CPG_ERRORRST_SEL2` and `CPG_ERROR_RST2` registers in the
CPG block must be configured. For example, setting `BIT(1)` in
`CPG_ERRORRST_SEL2` allows WDT1 to issue a system reset upon a watchdog
timer underflow. Similarly, `BIT(1)` in `CPG_ERROR_RST2` indicates whether
the system reset was caused by a WDT1 underflow. This functionality
enables the watchdog driver to configure the `CPG_ERRORRST_SEL2` register
and determine whether the system booted due to a `Power-on Reset` or a
`Watchdog Reset`.

To support this operation, add the `renesas,syscon-cpg-error-rst` property
to the WDT node. This property maps to the `syscon` CPG node, allowing the
watchdog driver to configure and retrieve the necessary reset information.

Additionally, this property is marked as required for the RZ/V2H(P) and
RZ/G3E SoC to ensure future compatibility and is explicitly disallowed
for other SoCs.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, this change doesnt break any ABI, as the subsequent driver patch
handles the case elegantly if the `syscon` node is missing to handle
backward compatibility.

v3->v4
- Updated commit message

v2->v3
- No change

v1->v2
- Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst`
- Updated commit message
---
 .../bindings/watchdog/renesas,wdt.yaml          | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
index 29ada89fdcdc..ca62ae8b1b0c 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.yaml
@@ -112,6 +112,19 @@ properties:
 
   timeout-sec: true
 
+  renesas,syscon-cpg-error-rst:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    description:
+      The first cell is a phandle to the SYSCON entry required to obtain
+      the current boot status. The second cell specifies the CPG_ERROR_RSTm
+      register offset within the SYSCON, and the third cell indicates the
+      bit within the CPG_ERROR_RSTm register.
+    items:
+      - items:
+          - description: Phandle to the CPG node
+          - description: The CPG_ERROR_RSTm register offset
+          - description: The bit within CPG_ERROR_RSTm register of interest
+
 required:
   - compatible
   - reg
@@ -182,7 +195,11 @@ allOf:
       properties:
         interrupts: false
         interrupt-names: false
+      required:
+        - renesas,syscon-cpg-error-rst
     else:
+      properties:
+        renesas,syscon-cpg-error-rst: false
       required:
         - interrupts
 
-- 
2.43.0

Re: [PATCH v4 5/9] dt-bindings: watchdog: renesas: Document `renesas,syscon-cpg-error-rst` property

[Rob Herring (Arm)]

On Mon, 10 Feb 2025 18:49:06 +0000, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> The CPG block in the RZ/V2H(P) and RZ/G3E SoCs includes Error Reset Select
> Registers (`CPG_ERRORRST_SELm`) and Error Reset Registers
> (`CPG_ERROR_RSTm`). The `CPG_ERRORRST_SELm` register must be configured to
> trigger a system reset in response to specific error conditions, while the
> `CPG_ERROR_RSTm` registers store the error interrupt factors that caused
> the system reset.
> 
> For the watchdog IP to trigger a system reset on a watchdog timer
> underflow, the `CPG_ERRORRST_SEL2` and `CPG_ERROR_RST2` registers in the
> CPG block must be configured. For example, setting `BIT(1)` in
> `CPG_ERRORRST_SEL2` allows WDT1 to issue a system reset upon a watchdog
> timer underflow. Similarly, `BIT(1)` in `CPG_ERROR_RST2` indicates whether
> the system reset was caused by a WDT1 underflow. This functionality
> enables the watchdog driver to configure the `CPG_ERRORRST_SEL2` register
> and determine whether the system booted due to a `Power-on Reset` or a
> `Watchdog Reset`.
> 
> To support this operation, add the `renesas,syscon-cpg-error-rst` property
> to the WDT node. This property maps to the `syscon` CPG node, allowing the
> watchdog driver to configure and retrieve the necessary reset information.
> 
> Additionally, this property is marked as required for the RZ/V2H(P) and
> RZ/G3E SoC to ensure future compatibility and is explicitly disallowed
> for other SoCs.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> Note, this change doesnt break any ABI, as the subsequent driver patch
> handles the case elegantly if the `syscon` node is missing to handle
> backward compatibility.
> 
> v3->v4
> - Updated commit message
> 
> v2->v3
> - No change
> 
> v1->v2
> - Renamed `renesas,r9a09g057-syscon-wdt-errorrst` to `renesas,syscon-cpg-error-rst`
> - Updated commit message
> ---
>  .../bindings/watchdog/renesas,wdt.yaml          | 17 +++++++++++++++++
>  1 file changed, 17 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH v4 6/9] watchdog: rzv2h_wdt: Add support to retrieve the bootstatus information

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

On the RZ/V2H(P) SoC we can determine if the current boot is due to
`Power-on-Reset` or due to the `Watchdog`. The information used to
determine this is present on the CPG block.

The CPG_ERROR_RSTm(m = 2 - 8) registers are set in response to an error
interrupt causing an reset. CPG_ERROR_RST2[ERROR_RST0/1/2] is set if there
was an underflow/overflow on WDT1 causing an error interrupt.

To fetch this information from CPG block `syscon` is used and bootstatus
field in the watchdog device is updated based on the
CPG_ERROR_RST2[ERROR_RST0/1/2] bit. Upon consumig
CPG_ERROR_RST2[ERROR_RST0/1/2] bit we clear it.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Note, this change doesnt break any ABI, if the `syscon` node is missing
the driver probe continues further to handle backward compatibility.

v3->v4
- called of_node_put() for args.np

v2->v3
- No change

v1->v2
- Returned ret in error path instead of -EINVAL
- Dropped unnecessar regmap_read
---
 drivers/watchdog/rzv2h_wdt.c | 40 ++++++++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index 8defd0241213..c9bdaa8f2e3a 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -4,14 +4,17 @@
  *
  * Copyright (C) 2024 Renesas Electronics Corporation.
  */
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/delay.h>
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/regmap.h>
 #include <linux/reset.h>
 #include <linux/units.h>
 #include <linux/watchdog.h>
@@ -40,6 +43,9 @@
 
 #define WDT_DEFAULT_TIMEOUT	60U
 
+#define CPG_ERROR_RST2(x)	BIT(x)
+#define CPG_ERROR_RST2_WEN(x)	BIT((x) + 16)
+
 static bool nowayout = WATCHDOG_NOWAYOUT;
 module_param(nowayout, bool, 0);
 MODULE_PARM_DESC(nowayout, "Watchdog cannot be stopped once started (default="
@@ -206,9 +212,42 @@ static const struct watchdog_ops rzv2h_wdt_ops = {
 static int rzv2h_wdt_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
+	struct device_node *np = dev->of_node;
 	struct rzv2h_wdt_priv *priv;
+	unsigned int bootstatus = 0;
+	struct regmap *syscon;
 	int ret;
 
+	/* Do not error out to maintain old DT compatibility */
+	syscon = syscon_regmap_lookup_by_phandle(np, "renesas,syscon-cpg-error-rst");
+	if (!IS_ERR(syscon)) {
+		struct of_phandle_args args;
+		u32 offset;
+		u32 val;
+		u8 bit;
+
+		ret = of_parse_phandle_with_fixed_args(np, "renesas,syscon-cpg-error-rst",
+						       2, 0, &args);
+		if (ret)
+			return ret;
+
+		offset = args.args[0];
+		bit = args.args[1];
+		of_node_put(args.np);
+		ret = regmap_read(syscon, offset, &val);
+		if (ret)
+			return ret;
+
+		if (val & CPG_ERROR_RST2(bit)) {
+			ret = regmap_write(syscon, offset,
+					   CPG_ERROR_RST2(bit) |
+					   CPG_ERROR_RST2_WEN(bit));
+			if (ret)
+				return ret;
+		}
+		bootstatus = val & CPG_ERROR_RST2(bit) ? WDIOF_CARDRESET : 0;
+	}
+
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
@@ -243,6 +282,7 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 	priv->wdev.info = &rzv2h_wdt_ident;
 	priv->wdev.ops = &rzv2h_wdt_ops;
 	priv->wdev.parent = dev;
+	priv->wdev.bootstatus = bootstatus;
 	watchdog_set_drvdata(&priv->wdev, priv);
 	watchdog_set_nowayout(&priv->wdev, nowayout);
 	watchdog_stop_on_unregister(&priv->wdev);
-- 
2.43.0

[PATCH v4 7/9] watchdog: rzv2h_wdt: Configure CPG_ERRORRST_SEL2 register

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Currently, the watchdog driver relies on TF-A/U-Boot to configure the
`CPG_ERRORRST_SEL2` register. This register must be set correctly to
ensure a reset request is issued upon watchdog timer (WDT) underflow.

Now that the driver has access to the `syscon` handle for CPG, configure
`CPG_ERRORRST_SEL2` directly instead of depending on firmware. This
improves robustness by ensuring the required configuration is applied
within the driver itself.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- New patch
---
 drivers/watchdog/rzv2h_wdt.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/drivers/watchdog/rzv2h_wdt.c b/drivers/watchdog/rzv2h_wdt.c
index c9bdaa8f2e3a..04b8ee899353 100644
--- a/drivers/watchdog/rzv2h_wdt.c
+++ b/drivers/watchdog/rzv2h_wdt.c
@@ -43,6 +43,10 @@
 
 #define WDT_DEFAULT_TIMEOUT	60U
 
+#define CPG_ERRORRST_SEL2(x)	((x) - 0x3c)
+#define CPG_ERRRSTSELx(x)	BIT(x)
+#define CPG_ERRRSTSELx_WEN(x)	BIT((x) + 16)
+
 #define CPG_ERROR_RST2(x)	BIT(x)
 #define CPG_ERROR_RST2_WEN(x)	BIT((x) + 16)
 
@@ -246,6 +250,16 @@ static int rzv2h_wdt_probe(struct platform_device *pdev)
 				return ret;
 		}
 		bootstatus = val & CPG_ERROR_RST2(bit) ? WDIOF_CARDRESET : 0;
+
+		/*
+		 * configure CPG_ERRORRST_SEL2 register to issue a reset request
+		 * upon WDT underflow
+		 */
+		ret = regmap_write(syscon, CPG_ERRORRST_SEL2(offset),
+				   CPG_ERRRSTSELx(bit) |
+				   CPG_ERRRSTSELx_WEN(bit));
+		if (ret)
+			return ret;
 	}
 
 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
-- 
2.43.0

Re: [PATCH v4 7/9] watchdog: rzv2h_wdt: Configure CPG_ERRORRST_SEL2 register

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 10 Feb 2025 at 19:49, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Currently, the watchdog driver relies on TF-A/U-Boot to configure the
> `CPG_ERRORRST_SEL2` register. This register must be set correctly to
> ensure a reset request is issued upon watchdog timer (WDT) underflow.
>
> Now that the driver has access to the `syscon` handle for CPG, configure
> `CPG_ERRORRST_SEL2` directly instead of depending on firmware. This
> improves robustness by ensuring the required configuration is applied
> within the driver itself.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Thanks for your patch!

IMHO doing it in the firmware stack is actually a good thing, as the
watchdog policy is system-wide, and thus goes beyond Linux running on
the application cores.

That is also the reason why commit 76b1c5b218f31811 ("[TEST] soc:
renesas: rcar-rst: Enable WDT reset on early R-Car V4M") is only
part of renesas-drivers[1], and not planned for upstream.  The sole
exception on modern R-Car is R-Car V3U, cfr. commit cb9a39aacd3d6387
("soc: renesas: rcar-rst: Allow WDT reset on R-Car V3U")[2].

[1] https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git/commit/?h=renesas-drivers-2025-02-18-v6.14-rc3&id=76b1c5b218f31811a7aaca588d3ec4ba584b7bf2
[2] https://elixir.bootlin.com/linux/v6.13.3/source/drivers/soc/renesas/rcar-rst.c#L76

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH v4 8/9] arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst` property to WDT node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `renesas,syscon-cpg-error-rst` property to WDT node, to
determine whether the current boot resulted from a `Power-on Reset`
or a `Watchdog Reset`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v2->v3
- No change

v1->v2
- No change
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index acc9c512fbab..4d5baed02fda 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -367,6 +367,7 @@ wdt0: watchdog@11c00400 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x75>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 0>;
 			status = "disabled";
 		};
 
@@ -377,6 +378,7 @@ wdt1: watchdog@14400000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x76>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;
 			status = "disabled";
 		};
 
@@ -387,6 +389,7 @@ wdt2: watchdog@13000000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x77>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 2>;
 			status = "disabled";
 		};
 
@@ -397,6 +400,7 @@ wdt3: watchdog@13000400 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x78>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 3>;
 			status = "disabled";
 		};
 
-- 
2.43.0

[PATCH v4 9/9] arm64: dts: renesas: r9a09g047: Add `renesas,syscon-cpg-error-rst` property to WDT node

[Prabhakar]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add `renesas,syscon-cpg-error-rst` property to WDT node, to determine
whether the current boot resulted from a `Power-on Reset` or a
`Watchdog Reset`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v3->v4
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g047.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
index c366bd2667ff..d5d7b390fac9 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g047.dtsi
@@ -189,6 +189,7 @@ wdt1: watchdog@14400000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x76>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 1>;
 			status = "disabled";
 		};
 
@@ -199,6 +200,7 @@ wdt2: watchdog@13000000 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x77>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 2>;
 			status = "disabled";
 		};
 
@@ -209,6 +211,7 @@ wdt3: watchdog@13000400 {
 			clock-names = "pclk", "oscclk";
 			resets = <&cpg 0x78>;
 			power-domains = <&cpg>;
+			renesas,syscon-cpg-error-rst = <&cpg 0xb40 3>;
 			status = "disabled";
 		};
 
-- 
2.43.0

Re: [PATCH v4 0/9] Add support to configure CPG block for watchdog on RZ/V2H(P) and RZ/G3E SoCs

[Lad, Prabhakar]

Hi All,

On Mon, Feb 10, 2025 at 6:49 PM Prabhakar <prabhakar.csengg@gmail.com> wrote:
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> This patch series adds SYSCON support to configure and retrieve boot
> status information from the CPG block for the RZ/V2H(P) and RZ/G3E SoCs.
> Summary of Changes,
>
>     Clock:
>         Add syscon compatible support to the CPG block in bindings and
>         device trees.
>
>     Watchdog:
>         Document the renesas,r9a09g057-syscon-wdt-errorrst property.
>         Update the watchdog driver to fetch and report boot status via
>         Error Reset Registers (CPG_ERROR_RSTm) and configure the
>         CPG_ERRORRST_SEL2 register.
>
>     Device Tree:
>         -Add the syscon property to CPG nodes in R9A09G057 and R9A09G047
>          SoC DTSI.
>         -Add the renesas,syscon-cpg-error-rst property to WDT nodes in
>          R9A09G057 and R9A09G047 SoC DTSI.
>
> v3->v4
> - Added support to configure CPG_ERRORRST_SEL2 register
> - Updated commit messages
>
> v2->v3
> - Updated comment section to mention there aren't any ABI breakages with
>   this patch series.
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (9):
>   dt-bindings: clock: rzv2h-cpg: Add syscon compatible for CPG
>   clk: renesas: Kconfig: Select MFD_SYSCON for RZ/V2H(P) family driver
>   arm64: dts: renesas: r9a09g047: Add `syscon` compatible for CPG node
>   arm64: dts: renesas: r9a09g057: Add `syscon` compatible for CPG node
>   dt-bindings: watchdog: renesas: Document
>     `renesas,syscon-cpg-error-rst` property
>   watchdog: rzv2h_wdt: Add support to retrieve the bootstatus
>     information
>   watchdog: rzv2h_wdt: Configure CPG_ERRORRST_SEL2 register
>   arm64: dts: renesas: r9a09g057: Add `renesas,syscon-cpg-error-rst`
>     property to WDT node
>   arm64: dts: renesas: r9a09g047: Add `renesas,syscon-cpg-error-rst`
>     property to WDT node
>
Gentle ping.


Cheers,
Prabhakar

Re: [PATCH v4 0/9] Add support to configure CPG block for watchdog on RZ/V2H(P) and RZ/G3E SoCs

[Geert Uytterhoeven]

Hi Prabhakar,

On Mon, 10 Feb 2025 at 19:49, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> This patch series adds SYSCON support to configure and retrieve boot
> status information from the CPG block for the RZ/V2H(P) and RZ/G3E SoCs.
> Summary of Changes,

Wasn't the plan to use a DT property under /chosen instead?
(Yes, I go to great lengths to avoid reviewing and accepting patches
 adding syscon compatible values anywhere ;-)

> v3->v4
> - Added support to configure CPG_ERRORRST_SEL2 register

Oh, I  guess that's the reason why you changed your mind.
I will reply to that patch...

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds