From: Bjorn Andersson <andersson@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Subject: Re: (subset) [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits
Date: Wed, 26 Feb 2025 07:40:45 -0600 [thread overview]
Message-ID: <174057724682.237840.3212969107242689758.b4-ty@kernel.org> (raw)
In-Reply-To: <20250203-topic-x1p4_dts-v2-0-72cd4cdc767b@oss.qualcomm.com>
On Mon, 03 Feb 2025 15:43:19 +0100, Konrad Dybcio wrote:
> X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is
> actually different and it's not a fused down part.
>
> Introduce the DTS bits required to support it by mostly reusing the
> X1E SoC and CRD DTSIs. The most notable differences from our software
> PoV are a different GPU (support for which will be added later), 4
> less CPUs and some nuances in the PCIe hardware.
>
> [...]
Applied, thanks!
[4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
commit: 62ca6669d62eb554eb467f2953cabb4238e18823
[5/6] arm64: dts: qcom: Commonize X1 CRD DTSI
commit: fbf5e007588f3f2bace84309b4a0d428ad619322
[6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD
commit: f08edb5299166b7c6d4eae439b1d3f81c31ba50e
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
prev parent reply other threads:[~2025-02-26 13:40 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-03 14:43 Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 1/6] dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 2/6] dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints Konrad Dybcio
2025-02-04 8:16 ` Krzysztof Kozlowski
2025-02-03 14:43 ` [PATCH v2 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 5/6] arm64: dts: qcom: Commonize X1 CRD DTSI Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD Konrad Dybcio
2025-02-10 17:21 ` (subset) [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits Vinod Koul
2025-02-26 13:40 ` Bjorn Andersson [this message]
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