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From: Konrad Dybcio <konradybcio@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
	 Kishon Vijay Abraham I <kishon@kernel.org>,
	Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	 Konrad Dybcio <konradybcio@kernel.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
	 linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
	 devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	 Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	 Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
	 Jens Glathe <jens.glathe@oldschoolsolutions.biz>
Subject: [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits
Date: Mon, 03 Feb 2025 15:43:19 +0100	[thread overview]
Message-ID: <20250203-topic-x1p4_dts-v2-0-72cd4cdc767b@oss.qualcomm.com> (raw)

X1P42100 is a(n indirect) derivative of X1E80100 - the silicon is
actually different and it's not a fused down part.

Introduce the DTS bits required to support it by mostly reusing the
X1E SoC and CRD DTSIs. The most notable differences from our software
PoV are a different GPU (support for which will be added later), 4
less CPUs and some nuances in the PCIe hardware.

This series very strictly depends on the NOCSR PCIe PHY reset patches.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Changes in v2:
- pick up tags (added Jens's t-b where it made sense)
- don't add & instantly delete a line in patches 2->3
- make patch 2 do what its commit message says
- Link to v1: https://lore.kernel.org/r/20250125-topic-x1p4_dts-v1-0-02659a08b044@oss.qualcomm.com

---
Konrad Dybcio (6):
      dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY
      dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints
      phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY
      arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets
      arm64: dts: qcom: Commonize X1 CRD DTSI
      arm64: dts: qcom: Add X1P42100 SoC and CRD

 .../bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml   |    9 +-
 arch/arm64/boot/dts/qcom/Makefile                  |    1 +
 .../dts/qcom/{x1e80100-crd.dts => x1-crd.dtsi}     |    7 -
 arch/arm64/boot/dts/qcom/x1e80100-crd.dts          | 1270 +-------------------
 arch/arm64/boot/dts/qcom/x1e80100-pmics.dtsi       |    2 +-
 arch/arm64/boot/dts/qcom/x1e80100.dtsi             |   44 +-
 arch/arm64/boot/dts/qcom/x1p42100-crd.dts          |   17 +
 arch/arm64/boot/dts/qcom/x1p42100.dtsi             |   81 ++
 drivers/phy/qualcomm/phy-qcom-qmp-pcie.c           |   18 +
 9 files changed, 148 insertions(+), 1301 deletions(-)
---
base-commit: e2ed2f6a484c2779f1f4fa873cd67f8baa10fc9c
change-id: 20250125-topic-x1p4_dts-3b9509bce3a3
prerequisite-message-id: 20250121094140.4006801-1-quic_wenbyao@quicinc.com
prerequisite-patch-id: 719a1c1319a8f25be57f1e9bc68887684ff0d7cd
prerequisite-patch-id: 44ff71b8033fc91867a83a2f8f063fd0d9951d5e

Best regards,
-- 
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>


             reply	other threads:[~2025-02-03 14:43 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-02-03 14:43 Konrad Dybcio [this message]
2025-02-03 14:43 ` [PATCH v2 1/6] dt-bindings: phy: qcom,qmp-pcie: Add X1P42100 PCIe Gen4x4 PHY Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 2/6] dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints Konrad Dybcio
2025-02-04  8:16   ` Krzysztof Kozlowski
2025-02-03 14:43 ` [PATCH v2 3/6] phy: qcom: qmp-pcie: Add X1P42100 Gen4x4 PHY Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 4/6] arm64: dts: qcom: x1e80100: Wire up PCIe PHY NOCSR resets Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 5/6] arm64: dts: qcom: Commonize X1 CRD DTSI Konrad Dybcio
2025-02-03 14:43 ` [PATCH v2 6/6] arm64: dts: qcom: Add X1P42100 SoC and CRD Konrad Dybcio
2025-02-10 17:21 ` (subset) [PATCH v2 0/6] X1P42100 DT and PCIe PHY bits Vinod Koul
2025-02-26 13:40 ` Bjorn Andersson

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