* [PATCH 1/2] drivers/edac: Add L1 and L2 error detection for A53, A57 and A72
2025-04-11 22:08 [v7 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
@ 2025-04-11 22:08 ` Vijay Balakrishna
2025-04-11 22:08 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-04-13 20:39 ` [v7 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Borislav Petkov
2 siblings, 0 replies; 5+ messages in thread
From: Vijay Balakrishna @ 2025-04-11 22:08 UTC (permalink / raw)
To: Borislav Petkov, Tony Luck, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: James Morse, Mauro Carvalho Chehab, Robert Richter, linux-edac,
linux-kernel, Tyler Hicks, Marc Zyngier, Sascha Hauer,
Lorenzo Pieralisi, devicetree, Vijay Balakrishna
From: Sascha Hauer <s.hauer@pengutronix.de>
The Cortex A53, A57 and A72 cores have error detection capabilities for
the L1/L2 Caches, this patch adds a driver for them. The selected errors
to detect/report have compatible bit assignments concerning CPU/L2 memory
error syndrome registers.
Unfortunately there is no robust way to inject errors into the caches,
so this driver doesn't contain any code to actually test it. It has
been tested though with code taken from an older version [1] of this
driver. For reasons stated in thread [1], the error injection code is
not suitable for mainline, so it is removed from the driver.
[1] https://lore.kernel.org/all/1521073067-24348-1-git-send-email-york.sun@nxp.com/#t
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Co-developed-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
---
drivers/edac/Kconfig | 9 ++
drivers/edac/Makefile | 1 +
drivers/edac/cortex_arm64_l1_l2.c | 232 ++++++++++++++++++++++++++++++
3 files changed, 242 insertions(+)
create mode 100644 drivers/edac/cortex_arm64_l1_l2.c
diff --git a/drivers/edac/Kconfig b/drivers/edac/Kconfig
index 19ad3c3b675d..20c15a18437f 100644
--- a/drivers/edac/Kconfig
+++ b/drivers/edac/Kconfig
@@ -576,4 +576,13 @@ config EDAC_LOONGSON
errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
are compatible.
+config EDAC_CORTEX_ARM64_L1_L2
+ tristate "ARM Cortex A72/A57/A53"
+ depends on ARM64
+ help
+ Support for L1/L2 cache error detection is provided for ARM Cortex
+ A72, A57, and A53 processors. The selected subset of errors is common
+ across these three MPCore processors, featuring compatible bit
+ assignments in their CPU/L2 memory error syndrome registers.
+
endif # EDAC
diff --git a/drivers/edac/Makefile b/drivers/edac/Makefile
index a8f2d8f6c894..157062410e61 100644
--- a/drivers/edac/Makefile
+++ b/drivers/edac/Makefile
@@ -88,3 +88,4 @@ obj-$(CONFIG_EDAC_NPCM) += npcm_edac.o
obj-$(CONFIG_EDAC_ZYNQMP) += zynqmp_edac.o
obj-$(CONFIG_EDAC_VERSAL) += versal_edac.o
obj-$(CONFIG_EDAC_LOONGSON) += loongson_edac.o
+obj-$(CONFIG_EDAC_CORTEX_ARM64_L1_L2) += cortex_arm64_l1_l2.o
diff --git a/drivers/edac/cortex_arm64_l1_l2.c b/drivers/edac/cortex_arm64_l1_l2.c
new file mode 100644
index 000000000000..650a7b10d24d
--- /dev/null
+++ b/drivers/edac/cortex_arm64_l1_l2.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cortex A72, A57 and A53 EDAC L1 and L2 cache error detection
+ *
+ * Copyright (c) 2020 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
+ *
+ * Based on Code from:
+ * Copyright (c) 2018, NXP Semiconductor
+ * Author: York Sun <york.sun@nxp.com>
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/bitfield.h>
+#include <asm/smp_plat.h>
+
+#include "edac_module.h"
+
+#define DRVNAME "cortex-arm64-edac"
+
+#define CPUMERRSR_EL1_RAMID GENMASK(30, 24)
+
+#define CPUMERRSR_EL1_VALID BIT(31)
+#define CPUMERRSR_EL1_FATAL BIT(63)
+
+#define L1_I_TAG_RAM 0x00
+#define L1_I_DATA_RAM 0x01
+#define L1_D_TAG_RAM 0x08
+#define L1_D_DATA_RAM 0x09
+#define TLB_RAM 0x18
+
+#define L2MERRSR_EL1_CPUID_WAY GENMASK(21, 18)
+
+#define L2MERRSR_EL1_VALID BIT(31)
+#define L2MERRSR_EL1_FATAL BIT(63)
+
+struct merrsr {
+ u64 cpumerr;
+ u64 l2merr;
+};
+
+#define MESSAGE_SIZE 64
+
+#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2)
+#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3)
+
+static struct cpumask compat_mask;
+
+static void report_errors(struct edac_device_ctl_info *edac_ctl, int cpu,
+ struct merrsr *merrsr)
+{
+ char msg[MESSAGE_SIZE];
+ u64 cpumerr = merrsr->cpumerr;
+ u64 l2merr = merrsr->l2merr;
+
+ if (cpumerr & CPUMERRSR_EL1_VALID) {
+ const char *str;
+ bool fatal = cpumerr & CPUMERRSR_EL1_FATAL;
+
+ switch (FIELD_GET(CPUMERRSR_EL1_RAMID, cpumerr)) {
+ case L1_I_TAG_RAM:
+ str = "L1-I Tag RAM";
+ break;
+ case L1_I_DATA_RAM:
+ str = "L1-I Data RAM";
+ break;
+ case L1_D_TAG_RAM:
+ str = "L1-D Tag RAM";
+ break;
+ case L1_D_DATA_RAM:
+ str = "L1-D Data RAM";
+ break;
+ case TLB_RAM:
+ str = "TLB RAM";
+ break;
+ default:
+ str = "Unspecified";
+ break;
+ }
+
+ snprintf(msg, MESSAGE_SIZE, "%s %s error(s) on CPU %d",
+ str, fatal ? "fatal" : "correctable", cpu);
+
+ if (fatal)
+ edac_device_handle_ue(edac_ctl, cpu, 0, msg);
+ else
+ edac_device_handle_ce(edac_ctl, cpu, 0, msg);
+ }
+
+ if (l2merr & L2MERRSR_EL1_VALID) {
+ bool fatal = l2merr & L2MERRSR_EL1_FATAL;
+
+ snprintf(msg, MESSAGE_SIZE, "L2 %s error(s) on CPU %d CPUID/WAY 0x%x",
+ fatal ? "fatal" : "correctable", cpu,
+ FIELD_GET(L2MERRSR_EL1_CPUID_WAY, l2merr));
+ if (fatal)
+ edac_device_handle_ue(edac_ctl, cpu, 1, msg);
+ else
+ edac_device_handle_ce(edac_ctl, cpu, 1, msg);
+ }
+}
+
+static void read_errors(void *data)
+{
+ struct merrsr *merrsr = data;
+
+ merrsr->cpumerr = read_sysreg_s(SYS_CPUMERRSR_EL1);
+ if (merrsr->cpumerr & CPUMERRSR_EL1_VALID) {
+ write_sysreg_s(0, SYS_CPUMERRSR_EL1);
+ isb();
+ }
+ merrsr->l2merr = read_sysreg_s(SYS_L2MERRSR_EL1);
+ if (merrsr->l2merr & L2MERRSR_EL1_VALID) {
+ write_sysreg_s(0, SYS_L2MERRSR_EL1);
+ isb();
+ }
+}
+
+static void cortex_arm64_edac_check(struct edac_device_ctl_info *edac_ctl)
+{
+ struct merrsr merrsr;
+ int cpu;
+
+ for_each_cpu_and(cpu, cpu_online_mask, &compat_mask) {
+ smp_call_function_single(cpu, read_errors, &merrsr, true);
+ report_errors(edac_ctl, cpu, &merrsr);
+ }
+}
+
+static int cortex_arm64_edac_probe(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_ctl;
+ struct device *dev = &pdev->dev;
+ int rc;
+
+ edac_ctl = edac_device_alloc_ctl_info(0, "cpu",
+ num_possible_cpus(), "L", 2, 1, NULL, 0,
+ edac_device_alloc_index());
+ if (!edac_ctl)
+ return -ENOMEM;
+
+ edac_ctl->edac_check = cortex_arm64_edac_check;
+ edac_ctl->dev = dev;
+ edac_ctl->mod_name = dev_name(dev);
+ edac_ctl->dev_name = dev_name(dev);
+ edac_ctl->ctl_name = DRVNAME;
+ dev_set_drvdata(dev, edac_ctl);
+
+ rc = edac_device_add_device(edac_ctl);
+ if (rc)
+ goto out_dev;
+
+ return 0;
+
+out_dev:
+ edac_device_free_ctl_info(edac_ctl);
+
+ return rc;
+}
+
+static int cortex_arm64_edac_remove(struct platform_device *pdev)
+{
+ struct edac_device_ctl_info *edac_ctl = dev_get_drvdata(&pdev->dev);
+
+ edac_device_del_device(edac_ctl->dev);
+ edac_device_free_ctl_info(edac_ctl);
+
+ return 0;
+}
+
+static const struct of_device_id cortex_arm64_edac_of_match[] = {
+ { .compatible = "arm,cortex-a53" },
+ { .compatible = "arm,cortex-a57" },
+ { .compatible = "arm,cortex-a72" },
+ {}
+};
+MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match);
+
+static struct platform_driver cortex_arm64_edac_driver = {
+ .probe = cortex_arm64_edac_probe,
+ .remove = cortex_arm64_edac_remove,
+ .driver = {
+ .name = DRVNAME,
+ },
+};
+
+static int __init cortex_arm64_edac_driver_init(void)
+{
+ struct device_node *np;
+ int cpu;
+ struct platform_device *pdev;
+ int err;
+
+ for_each_possible_cpu(cpu) {
+ np = of_get_cpu_node(cpu, NULL);
+
+ if (!np) {
+ pr_warn("failed to find device node for cpu %d\n", cpu);
+ continue;
+ }
+ if (!of_match_node(cortex_arm64_edac_of_match, np))
+ continue;
+ if (!of_property_read_bool(np, "edac-enabled"))
+ continue;
+ cpumask_set_cpu(cpu, &compat_mask);
+ of_node_put(np);
+ }
+
+ if (cpumask_empty(&compat_mask))
+ return 0;
+
+ err = platform_driver_register(&cortex_arm64_edac_driver);
+ if (err)
+ return err;
+
+ pdev = platform_device_register_simple(DRVNAME, -1, NULL, 0);
+ if (IS_ERR(pdev)) {
+ pr_err("failed to register cortex arm64 edac device\n");
+ platform_driver_unregister(&cortex_arm64_edac_driver);
+ return PTR_ERR(pdev);
+ }
+
+ return 0;
+}
+
+device_initcall(cortex_arm64_edac_driver_init);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
+MODULE_DESCRIPTION("Cortex A72, A57 and A53 L1 and L2 cache EDAC driver");
--
2.49.0
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property
2025-04-11 22:08 [v7 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
2025-04-11 22:08 ` [PATCH 1/2] drivers/edac: " Vijay Balakrishna
@ 2025-04-11 22:08 ` Vijay Balakrishna
2025-04-13 20:39 ` [v7 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Borislav Petkov
2 siblings, 0 replies; 5+ messages in thread
From: Vijay Balakrishna @ 2025-04-11 22:08 UTC (permalink / raw)
To: Borislav Petkov, Tony Luck, Rob Herring, Krzysztof Kozlowski,
Conor Dooley
Cc: James Morse, Mauro Carvalho Chehab, Robert Richter, linux-edac,
linux-kernel, Tyler Hicks, Marc Zyngier, Sascha Hauer,
Lorenzo Pieralisi, devicetree, Vijay Balakrishna
From: Sascha Hauer <s.hauer@pengutronix.de>
Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And
Correction (EDAC) support on their L1 and L2 caches. This is implemented
in implementation defined registers, so usage of this functionality is
not safe in virtualized environments or when EL3 already uses these
registers. This patch adds a edac-enabled flag which can be explicitly
set when EDAC can be used.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
[vijayb: Added A72 to the commit message]
Signed-off-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
---
Documentation/devicetree/bindings/arm/cpus.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml
index 2e666b2a4dcd..d1dc0a843d07 100644
--- a/Documentation/devicetree/bindings/arm/cpus.yaml
+++ b/Documentation/devicetree/bindings/arm/cpus.yaml
@@ -331,6 +331,12 @@ properties:
corresponding to the index of an SCMI performance domain provider, must be
"perf".
+ edac-enabled:
+ $ref: /schemas/types.yaml#/definitions/flag
+ description:
+ Some CPUs support Error Detection And Correction (EDAC) on their L1 and
+ L2 caches. This flag marks this function as usable.
+
qcom,saw:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
--
2.49.0
^ permalink raw reply [flat|nested] 5+ messages in thread