Re: [PATCH] perf/x86/intel: Fix crashing bug in icl_update_topdown_event

Re: [PATCH] perf/x86/intel: Fix crashing bug in icl_update_topdown_event

[Liang, Kan]

Hi Peter and Ingo,

On 2025-06-12 10:38 a.m., kan.liang@linux.intel.com wrote:
> From: Kan Liang <kan.liang@linux.intel.com>
> 
> The perf_fuzzer found a hard-lock crash on a RaptorLake
> machine.
> 
> Oops: general protection fault, maybe for address 0xffff89aeceab400: 0000
> CPU: 23 UID: 0 PID: 0 Comm: swapper/23
> Tainted: [W]=WARN
> Hardware name: Dell Inc. Precision 9660/0VJ762
> RIP: 0010:native_read_pmc+0x7/0x40
> Code: cc e8 8d a9 01 00 48 89 03 5b cd cc cc cc cc 0f 1f ...
> RSP: 000:fffb03100273de8 EFLAGS: 00010046
> ....
> Call Trace:
>   <TASK>
>   icl_update_topdown_event+0x165/0x190
>   ? ktime_get+0x38/0xd0
>   intel_pmu_read_event+0xf9/0x210
>   __perf_event_read+0xf9/0x210
> 
> The CPUs 16-23 are e-core CPUs that don't support perf metrics feature.
> The icl_update_topdown_event() should not be invoked.
> 
> It's an regression of the commit f9bdf1f95339 ("perf/x86/intel: Avoid
> disable PMU if !cpuc->enabled in sample read"). The is_topdown_event()
> is mistakenly used to replace the is_topdown_count() to check if the
> topdown functions for the perf metrics feature should be invoked.
> The is_topdown_event() only checks the event encoding. It's possible
> that the same encoding 0x0400 is created on an e-core CPU (although
> there is no valid event with such encoding on e-core).
> The is_topdown_count() checks the PERF_X86_EVENT_TOPDOWN flag. Only
> when the topdown events require the perf metrics magic, the flag is set.
> 
> It should be a typo when merging the intel_pmu_auto_reload_read() and
> intel_pmu_read_topdown_event() in the commit.
> 
> Fixes: f9bdf1f95339 ("perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read")
> Reported-by: Vince Weaver <vincent.weaver@maine.edu>
> Closes: https://lore.kernel.org/lkml/352f0709-f026-cd45-e60c-60dfd97f73f3@maine.edu/
> Signed-off-by: Kan Liang <kan.liang@linux.intel.com>

Please help to add the tested-by tag from Vince if the patch looks good
to you.

Tested-by: Vince Weaver <vincent.weaver@maine.edu>

https://lore.kernel.org/lkml/da4d8a9a-66a4-32b4-0283-ef4687357349@maine.edu/

Thanks,
Kan> ---
>  arch/x86/events/intel/core.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index c60b6f199f51..38886cd7aa65 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2826,7 +2826,7 @@ static void intel_pmu_read_event(struct perf_event *event)
>  		 * If the PEBS counters snapshotting is enabled,
>  		 * the topdown event is available in PEBS records.
>  		 */
> -		if (is_topdown_event(event) && !is_pebs_counter_event_group(event))
> +		if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
>  			static_call(intel_pmu_update_topdown_event)(event, NULL);
>  		else
>  			intel_pmu_drain_pebs_buffer();

[tip: perf/urgent] perf/x86/intel: Fix crashing bug in icl_update_topdown_event

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     e49460a2d03fd8689ce5f7f2d79ff159734ad563
Gitweb:        https://git.kernel.org/tip/e49460a2d03fd8689ce5f7f2d79ff159734ad563
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 12 Jun 2025 07:38:18 -07:00
Committer:     Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 13 Jun 2025 08:54:21 +02:00

perf/x86/intel: Fix crashing bug in icl_update_topdown_event

The perf_fuzzer found a hard-lock crash on a RaptorLake machine.

  Oops: general protection fault, maybe for address 0xffff89aeceab400: 0000
  CPU: 23 UID: 0 PID: 0 Comm: swapper/23
  Tainted: [W]=WARN
  Hardware name: Dell Inc. Precision 9660/0VJ762
  RIP: 0010:native_read_pmc+0x7/0x40
  Code: cc e8 8d a9 01 00 48 89 03 5b cd cc cc cc cc 0f 1f ...
  RSP: 000:fffb03100273de8 EFLAGS: 00010046
  ....
  Call Trace:
    <TASK>
    icl_update_topdown_event+0x165/0x190
    ? ktime_get+0x38/0xd0
    intel_pmu_read_event+0xf9/0x210
    __perf_event_read+0xf9/0x210

The CPUs 16-23 are E-core CPUs that don't support perf metrics feature.
The icl_update_topdown_event() should not be invoked.

It's an regression of the commit f9bdf1f95339 ("perf/x86/intel: Avoid
disable PMU if !cpuc->enabled in sample read"). The is_topdown_event()
is mistakenly used to replace the is_topdown_count() to check if the
topdown functions for the perf metrics feature should be invoked.  The
is_topdown_event() only checks the event encoding. It's possible that
the same encoding 0x0400 is created on an e-core CPU (although there
is no valid event with such encoding on e-core).  The
is_topdown_count() checks the PERF_X86_EVENT_TOPDOWN flag. Only when
the topdown events require the perf metrics magic, the flag is set.

It should be a typo when merging the intel_pmu_auto_reload_read() and
intel_pmu_read_topdown_event() in the commit.

Fixes: f9bdf1f95339 ("perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read")
Closes: https://lore.kernel.org/lkml/352f0709-f026-cd45-e60c-60dfd97f73f3@maine.edu/
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Link: https://lore.kernel.org/r/20250612143818.2889040-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 741b229..c2fb729 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2826,7 +2826,7 @@ static void intel_pmu_read_event(struct perf_event *event)
 		 * If the PEBS counters snapshotting is enabled,
 		 * the topdown event is available in PEBS records.
 		 */
-		if (is_topdown_event(event) && !is_pebs_counter_event_group(event))
+		if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
 			static_call(intel_pmu_update_topdown_event)(event, NULL);
 		else
 			intel_pmu_drain_pebs_buffer();

[tip: perf/urgent] perf/x86/intel: Fix crash in icl_update_topdown_event()

[tip-bot2 for Kan Liang]

The following commit has been merged into the perf/urgent branch of tip:

Commit-ID:     b0823d5fbacb1c551d793cbfe7af24e0d1fa45ed
Gitweb:        https://git.kernel.org/tip/b0823d5fbacb1c551d793cbfe7af24e0d1fa45ed
Author:        Kan Liang <kan.liang@linux.intel.com>
AuthorDate:    Thu, 12 Jun 2025 07:38:18 -07:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 13 Jun 2025 09:38:06 +02:00

perf/x86/intel: Fix crash in icl_update_topdown_event()

The perf_fuzzer found a hard-lockup crash on a RaptorLake machine:

  Oops: general protection fault, maybe for address 0xffff89aeceab400: 0000
  CPU: 23 UID: 0 PID: 0 Comm: swapper/23
  Tainted: [W]=WARN
  Hardware name: Dell Inc. Precision 9660/0VJ762
  RIP: 0010:native_read_pmc+0x7/0x40
  Code: cc e8 8d a9 01 00 48 89 03 5b cd cc cc cc cc 0f 1f ...
  RSP: 000:fffb03100273de8 EFLAGS: 00010046
  ....
  Call Trace:
    <TASK>
    icl_update_topdown_event+0x165/0x190
    ? ktime_get+0x38/0xd0
    intel_pmu_read_event+0xf9/0x210
    __perf_event_read+0xf9/0x210

CPUs 16-23 are E-core CPUs that don't support the perf metrics feature.
The icl_update_topdown_event() should not be invoked on these CPUs.

It's a regression of commit:

  f9bdf1f95339 ("perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read")

The bug introduced by that commit is that the is_topdown_event() function
is mistakenly used to replace the is_topdown_count() call to check if the
topdown functions for the perf metrics feature should be invoked.

Fix it.

Fixes: f9bdf1f95339 ("perf/x86/intel: Avoid disable PMU if !cpuc->enabled in sample read")
Closes: https://lore.kernel.org/lkml/352f0709-f026-cd45-e60c-60dfd97f73f3@maine.edu/
Reported-by: Vince Weaver <vincent.weaver@maine.edu>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Tested-by: Vince Weaver <vincent.weaver@maine.edu>
Cc: stable@vger.kernel.org # v6.15+
Link: https://lore.kernel.org/r/20250612143818.2889040-1-kan.liang@linux.intel.com
---
 arch/x86/events/intel/core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 741b229..c2fb729 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2826,7 +2826,7 @@ static void intel_pmu_read_event(struct perf_event *event)
 		 * If the PEBS counters snapshotting is enabled,
 		 * the topdown event is available in PEBS records.
 		 */
-		if (is_topdown_event(event) && !is_pebs_counter_event_group(event))
+		if (is_topdown_count(event) && !is_pebs_counter_event_group(event))
 			static_call(intel_pmu_update_topdown_event)(event, NULL);
 		else
 			intel_pmu_drain_pebs_buffer();