* [PATCH 1/6] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 2/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Jayesh Choudhary
` (4 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
The system controller node manages the CTRL_MMR0 region.
Add serdes_ln_ctrl node which is used for controlling the SERDES lane mux.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index e9169eb358c1..344f4ffa0b82 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -5,6 +5,9 @@
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
*/
+#include <dt-bindings/mux/mux.h>
+#include <dt-bindings/mux/ti-serdes.h>
+
&cbass_main {
msmc_ram: sram@70000000 {
compatible = "mmio-sram";
@@ -26,6 +29,25 @@ l3cache-sram@200000 {
};
};
+ scm_conf: scm-conf@100000 {
+ compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
+ reg = <0x00 0x00100000 0x00 0x1c000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x00 0x00 0x00100000 0x1c000>;
+
+ serdes_ln_ctrl: mux-controller@4080 {
+ compatible = "mmio-mux";
+ #mux-control-cells = <1>;
+ mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */
+ <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */
+ <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */
+ <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */
+ <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */
+ <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */
+ };
+ };
+
gic500: interrupt-controller@1800000 {
compatible = "arm,gic-v3";
#address-cells = <2>;
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 2/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 1/6] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 3/6] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Jayesh Choudhary
` (3 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
J784S4 SoC has a Main CPSW2G instance of the CPSW Ethernet Switch.
Add the device-tree nodes for the Main CPSW2G instance and enable it.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 48 +++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 68 ++++++++++++++++++++++
2 files changed, 116 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index f33815953e77..aef6f53ae8ac 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -105,6 +105,30 @@ vdd_sd_dv: regulator-TLV71033 {
};
&main_pmx0 {
+ main_cpsw2g_pins_default: main-cpsw2g-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */
+ J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */
+ J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */
+ J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */
+ J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */
+ J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */
+ J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */
+ J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */
+ J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */
+ J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */
+ J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */
+ J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */
+ >;
+ };
+
+ main_cpsw2g_mdio_pins_default: main-cpsw2g-mdio-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */
+ J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */
+ >;
+ };
+
main_uart8_pins_default: main-uart8-pins-default {
pinctrl-single,pins = <
J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
@@ -253,3 +277,27 @@ &mcu_cpsw_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&mcu_phy0>;
};
+
+&main_cpsw1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_pins_default>;
+};
+
+&main_cpsw1_mdio {
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_cpsw2g_mdio_pins_default>;
+
+ main_phy0: ethernet-phy@0 {
+ reg = <0>;
+ ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
+ ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
+ ti,min-output-impedance;
+ };
+};
+
+&main_cpsw1_port1 {
+ status = "okay";
+ phy-mode = "rgmii-rxid";
+ phy-handle = <&main_phy0>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 344f4ffa0b82..35b2ee07549b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -36,6 +36,12 @@ scm_conf: scm-conf@100000 {
#size-cells = <1>;
ranges = <0x00 0x00 0x00100000 0x1c000>;
+ cpsw1_phy_gmii_sel: phy@4034 {
+ compatible = "ti,am654-phy-gmii-sel";
+ reg = <0x4034 0x4>;
+ #phy-cells = <1>;
+ };
+
serdes_ln_ctrl: mux-controller@4080 {
compatible = "mmio-mux";
#mux-control-cells = <1>;
@@ -777,6 +783,68 @@ cpts@310d0000 {
};
};
+ main_cpsw1: ethernet@c200000 {
+ compatible = "ti,j721e-cpsw-nuss";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ reg = <0x00 0xc200000 0x00 0x200000>;
+ reg-names = "cpsw_nuss";
+ ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>;
+ dma-coherent;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>;
+
+ dmas = <&main_udmap 0xc640>,
+ <&main_udmap 0xc641>,
+ <&main_udmap 0xc642>,
+ <&main_udmap 0xc643>,
+ <&main_udmap 0xc644>,
+ <&main_udmap 0xc645>,
+ <&main_udmap 0xc646>,
+ <&main_udmap 0xc647>,
+ <&main_udmap 0x4640>;
+ dma-names = "tx0", "tx1", "tx2", "tx3",
+ "tx4", "tx5", "tx6", "tx7",
+ "rx";
+
+ status = "disabled";
+
+ ethernet-ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ main_cpsw1_port1: port@1 {
+ reg = <1>;
+ label = "port1";
+ phys = <&cpsw1_phy_gmii_sel 1>;
+ ti,mac-only;
+ status = "disabled";
+ };
+ };
+
+ main_cpsw1_mdio: mdio@f00 {
+ compatible = "ti,cpsw-mdio", "ti,davinci_mdio";
+ reg = <0x00 0xf00 0x00 0x100>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&k3_clks 62 0>;
+ clock-names = "fck";
+ bus_freq = <1000000>;
+ };
+
+ cpts@3d000 {
+ compatible = "ti,am65-cpts";
+ reg = <0x00 0x3d000 0x00 0x400>;
+ clocks = <&k3_clks 62 3>;
+ clock-names = "cpts";
+ interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "cpts";
+ ti,cpts-ext-ts-inputs = <4>;
+ ti,cpts-periodic-outputs = <2>;
+ };
+ };
+
main_mcan0: can@2701000 {
compatible = "bosch,m_can";
reg = <0x00 0x02701000 0x00 0x200>,
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/6] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 1/6] arm64: dts: ti: k3-j784s4-main: Add system controller and SERDES lane mux Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 2/6] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node Jayesh Choudhary
` (2 subsequent siblings)
5 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Siddharth Vadapalli <s-vadapalli@ti.com>
J784S4 SoC has 4 Serdes instances along with their respective WIZ
instances. Add device-tree nodes for them and disable them by default.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 4 +
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 171 +++++++++++++++++++++
2 files changed, 175 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index aef6f53ae8ac..b1445b7c2aa8 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -301,3 +301,7 @@ &main_cpsw1_port1 {
phy-mode = "rgmii-rxid";
phy-handle = <&main_phy0>;
};
+
+&serdes_refclk {
+ clock-frequency = <100000000>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 35b2ee07549b..0cd692bc52e6 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -7,6 +7,15 @@
#include <dt-bindings/mux/mux.h>
#include <dt-bindings/mux/ti-serdes.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/phy/phy-ti.h>
+
+/ {
+ serdes_refclk: serdes-refclk {
+ #clock-cells = <0>;
+ compatible = "fixed-clock";
+ };
+};
&cbass_main {
msmc_ram: sram@70000000 {
@@ -440,6 +449,168 @@ main_sdhci1: mmc@4fb0000 {
status = "disabled";
};
+ serdes_wiz0: wiz@5060000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 404 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 404 2>, <&k3_clks 404 6>, <&k3_clks 404 5>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 404 6>;
+ assigned-clock-parents = <&k3_clks 404 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x5060000 0x00 0x5060000 0x10000>;
+
+ status = "disabled";
+
+ serdes0: serdes@5060000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05060000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz0 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz0 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz0 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 404 6>,
+ <&k3_clks 404 6>,
+ <&k3_clks 404 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz1: wiz@5070000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 405 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 405 2>, <&k3_clks 405 6>, <&k3_clks 405 5>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 405 6>;
+ assigned-clock-parents = <&k3_clks 405 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05070000 0x00 0x05070000 0x10000>;
+
+ status = "disabled";
+
+ serdes1: serdes@5070000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05070000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz1 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz1 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz1 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 405 6>,
+ <&k3_clks 405 6>,
+ <&k3_clks 405 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz2: wiz@5020000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 406 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 406 2>, <&k3_clks 406 6>, <&k3_clks 406 5>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 406 6>;
+ assigned-clock-parents = <&k3_clks 406 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05020000 0x00 0x05020000 0x10000>;
+
+ status = "disabled";
+
+ serdes2: serdes@5020000 {
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05020000 0x010000>;
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz2 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz2 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz2 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 406 6>,
+ <&k3_clks 406 6>,
+ <&k3_clks 406 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
+ serdes_wiz4: wiz@5050000 {
+ compatible = "ti,j784s4-wiz-10g";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ power-domains = <&k3_pds 407 TI_SCI_PD_EXCLUSIVE>;
+ clocks = <&k3_clks 407 2>, <&k3_clks 407 6>, <&k3_clks 407 5>, <&serdes_refclk>;
+ clock-names = "fck", "core_ref_clk", "core_ref1_clk", "ext_ref_clk";
+ assigned-clocks = <&k3_clks 407 6>;
+ assigned-clock-parents = <&k3_clks 407 10>;
+ num-lanes = <4>;
+ #reset-cells = <1>;
+ #clock-cells = <1>;
+ ranges = <0x05050000 0x00 0x05050000 0x10000>,
+ <0xa030a00 0x00 0xa030a00 0x40>; /* DPTX PHY */
+
+ status = "disabled";
+
+ serdes4: serdes@5050000 {
+ /*
+ * Note: we also map DPTX PHY registers as the Torrent
+ * needs to manage those.
+ */
+ compatible = "ti,j721e-serdes-10g";
+ reg = <0x05050000 0x010000>,
+ <0x0a030a00 0x40>; /* DPTX PHY */
+ reg-names = "torrent_phy";
+ resets = <&serdes_wiz4 0>;
+ reset-names = "torrent_reset";
+ clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PHY_EN_REFCLK>;
+ clock-names = "refclk", "phy_en_refclk";
+ assigned-clocks = <&serdes_wiz4 TI_WIZ_PLL0_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_PLL1_REFCLK>,
+ <&serdes_wiz4 TI_WIZ_REFCLK_DIG>;
+ assigned-clock-parents = <&k3_clks 407 6>,
+ <&k3_clks 407 6>,
+ <&k3_clks 407 6>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #clock-cells = <1>;
+
+ status = "disabled";
+ };
+ };
+
main_navss: bus@30000000 {
compatible = "simple-bus";
#address-cells = <2>;
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
` (2 preceding siblings ...)
2023-04-05 11:14 ` [PATCH 3/6] arm64: dts: ti: k3-j784s4: Add WIZ and SERDES PHY nodes Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
2023-04-05 16:37 ` Andrew Davis
2023-04-05 11:14 ` [PATCH 5/6] arm64: dts: ti: k3-j784s4-*: add DP & DP PHY Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 6/6] arm64: dts: ti: k3-j784s4-evm: Add DP0 Jayesh Choudhary
5 siblings, 1 reply; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Add DSS node for J784S4 SoC. DSS IP in J784S4
is same as DSS IP in J721E, so same compatible is
being used.
Also add assigned clks for DSS
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++
2 files changed, 66 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index b1445b7c2aa8..ccbfca76e9ae 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -305,3 +305,14 @@ &main_cpsw1_port1 {
&serdes_refclk {
clock-frequency = <100000000>;
};
+
+&dss {
+ assigned-clocks = <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ assigned-clock-parents = <&k3_clks 218 3>,
+ <&k3_clks 218 7>,
+ <&k3_clks 218 16>,
+ <&k3_clks 218 22>;
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 0cd692bc52e6..86ce6f6d4fc2 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1373,4 +1373,59 @@ main_spi7: spi@2170000 {
clocks = <&k3_clks 383 1>;
status = "disabled";
};
+
+ dss: dss@4a00000 {
+ compatible = "ti,j721e-dss";
+ reg =
+ <0x00 0x04a00000 0x00 0x10000>,
+ <0x00 0x04a10000 0x00 0x10000>,
+ <0x00 0x04b00000 0x00 0x10000>,
+ <0x00 0x04b10000 0x00 0x10000>,
+
+ <0x00 0x04a20000 0x00 0x10000>,
+ <0x00 0x04a30000 0x00 0x10000>,
+ <0x00 0x04a50000 0x00 0x10000>,
+ <0x00 0x04a60000 0x00 0x10000>,
+
+ <0x00 0x04a70000 0x00 0x10000>,
+ <0x00 0x04a90000 0x00 0x10000>,
+ <0x00 0x04ab0000 0x00 0x10000>,
+ <0x00 0x04ad0000 0x00 0x10000>,
+
+ <0x00 0x04a80000 0x00 0x10000>,
+ <0x00 0x04aa0000 0x00 0x10000>,
+ <0x00 0x04ac0000 0x00 0x10000>,
+ <0x00 0x04ae0000 0x00 0x10000>,
+ <0x00 0x04af0000 0x00 0x10000>;
+
+ reg-names = "common_m", "common_s0",
+ "common_s1", "common_s2",
+ "vidl1", "vidl2","vid1","vid2",
+ "ovr1", "ovr2", "ovr3", "ovr4",
+ "vp1", "vp2", "vp3", "vp4",
+ "wb";
+
+ clocks = <&k3_clks 218 0>,
+ <&k3_clks 218 2>,
+ <&k3_clks 218 5>,
+ <&k3_clks 218 14>,
+ <&k3_clks 218 18>;
+ clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
+
+ power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
+
+ interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "common_m",
+ "common_s0",
+ "common_s1",
+ "common_s2";
+
+ status = "disabled";
+
+ dss_ports: ports {
+ };
+ };
};
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node
2023-04-05 11:14 ` [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node Jayesh Choudhary
@ 2023-04-05 16:37 ` Andrew Davis
2023-04-06 11:00 ` Jayesh Choudhary
0 siblings, 1 reply; 9+ messages in thread
From: Andrew Davis @ 2023-04-05 16:37 UTC (permalink / raw)
To: Jayesh Choudhary, nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel
On 4/5/23 6:14 AM, Jayesh Choudhary wrote:
> From: Rahul T R <r-ravikumar@ti.com>
>
> Add DSS node for J784S4 SoC. DSS IP in J784S4
> is same as DSS IP in J721E, so same compatible is
> being used.
> Also add assigned clks for DSS
>
> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
> ---
> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++
The changes to `k3-j784s4-evm.dts` in this patch and the next all
need moved to the last patch in this series. All these changes
needed to enable the display in the EVM work together and so
should be one atomic step.
Andrew
> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> index b1445b7c2aa8..ccbfca76e9ae 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
> @@ -305,3 +305,14 @@ &main_cpsw1_port1 {
> &serdes_refclk {
> clock-frequency = <100000000>;
> };
> +
> +&dss {
> + assigned-clocks = <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + assigned-clock-parents = <&k3_clks 218 3>,
> + <&k3_clks 218 7>,
> + <&k3_clks 218 16>,
> + <&k3_clks 218 22>;
> +};
> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> index 0cd692bc52e6..86ce6f6d4fc2 100644
> --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
> @@ -1373,4 +1373,59 @@ main_spi7: spi@2170000 {
> clocks = <&k3_clks 383 1>;
> status = "disabled";
> };
> +
> + dss: dss@4a00000 {
> + compatible = "ti,j721e-dss";
> + reg =
> + <0x00 0x04a00000 0x00 0x10000>,
> + <0x00 0x04a10000 0x00 0x10000>,
> + <0x00 0x04b00000 0x00 0x10000>,
> + <0x00 0x04b10000 0x00 0x10000>,
> +
> + <0x00 0x04a20000 0x00 0x10000>,
> + <0x00 0x04a30000 0x00 0x10000>,
> + <0x00 0x04a50000 0x00 0x10000>,
> + <0x00 0x04a60000 0x00 0x10000>,
> +
> + <0x00 0x04a70000 0x00 0x10000>,
> + <0x00 0x04a90000 0x00 0x10000>,
> + <0x00 0x04ab0000 0x00 0x10000>,
> + <0x00 0x04ad0000 0x00 0x10000>,
> +
> + <0x00 0x04a80000 0x00 0x10000>,
> + <0x00 0x04aa0000 0x00 0x10000>,
> + <0x00 0x04ac0000 0x00 0x10000>,
> + <0x00 0x04ae0000 0x00 0x10000>,
> + <0x00 0x04af0000 0x00 0x10000>;
> +
> + reg-names = "common_m", "common_s0",
> + "common_s1", "common_s2",
> + "vidl1", "vidl2","vid1","vid2",
> + "ovr1", "ovr2", "ovr3", "ovr4",
> + "vp1", "vp2", "vp3", "vp4",
> + "wb";
> +
> + clocks = <&k3_clks 218 0>,
> + <&k3_clks 218 2>,
> + <&k3_clks 218 5>,
> + <&k3_clks 218 14>,
> + <&k3_clks 218 18>;
> + clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
> +
> + power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
> +
> + interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "common_m",
> + "common_s0",
> + "common_s1",
> + "common_s2";
> +
> + status = "disabled";
> +
> + dss_ports: ports {
> + };
> + };
> };
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node
2023-04-05 16:37 ` Andrew Davis
@ 2023-04-06 11:00 ` Jayesh Choudhary
0 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-06 11:00 UTC (permalink / raw)
To: Andrew Davis, nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel
Hello Andrew,
On 05/04/23 22:07, Andrew Davis wrote:
> On 4/5/23 6:14 AM, Jayesh Choudhary wrote:
>> From: Rahul T R <r-ravikumar@ti.com>
>>
>> Add DSS node for J784S4 SoC. DSS IP in J784S4
>> is same as DSS IP in J721E, so same compatible is
>> being used.
>> Also add assigned clks for DSS
>>
>> Signed-off-by: Rahul T R <r-ravikumar@ti.com>
>> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
>> ---
>> arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 11 +++++
>
>
> The changes to `k3-j784s4-evm.dts` in this patch and the next all
> need moved to the last patch in this series. All these changes
> needed to enable the display in the EVM work together and so
> should be one atomic step.
>
> Andrew
Okay. Will fix this in v2.
-Jayesh
>
>> arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 55 ++++++++++++++++++++++
>> 2 files changed, 66 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> index b1445b7c2aa8..ccbfca76e9ae 100644
>> --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
>> @@ -305,3 +305,14 @@ &main_cpsw1_port1 {
>> &serdes_refclk {
>> clock-frequency = <100000000>;
>> };
[...]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 5/6] arm64: dts: ti: k3-j784s4-*: add DP & DP PHY
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
` (3 preceding siblings ...)
2023-04-05 11:14 ` [PATCH 4/6] arm64: dts: ti: k3-j784s4-*: Add DSS node Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
2023-04-05 11:14 ` [PATCH 6/6] arm64: dts: ti: k3-j784s4-evm: Add DP0 Jayesh Choudhary
5 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Add DT nodes for DisplayPort and DisplayPort PHY.
The DP is Cadence MHDP 8546 and the PHY is a
Cadence Torrent PHY with TI WIZ wrapper.
Also add pinmux required for DP HPD.
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 24 ++++++++++++++++++++++
arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 22 ++++++++++++++++++++
2 files changed, 46 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index ccbfca76e9ae..2b414fd973d0 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -163,6 +163,12 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
>;
};
+
+ dp0_pins_default: dp0-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
+ >;
+ };
};
&wkup_pmx0 {
@@ -316,3 +322,21 @@ &dss {
<&k3_clks 218 16>,
<&k3_clks 218 22>;
};
+
+&serdes4 {
+ serdes4_dp_link: phy@0 {
+ reg = <0>;
+ cdns,num-lanes = <4>;
+ #phy-cells = <0>;
+ cdns,phy-type = <PHY_TYPE_DP>;
+ resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>,
+ <&serdes_wiz4 3>, <&serdes_wiz4 4>;
+ };
+};
+
+&mhdp {
+ pinctrl-names = "default";
+ pinctrl-0 = <&dp0_pins_default>;
+ phys = <&serdes4_dp_link>;
+ phy-names = "dpphy";
+};
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index 86ce6f6d4fc2..fc6071c16188 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -1374,6 +1374,28 @@ main_spi7: spi@2170000 {
status = "disabled";
};
+ mhdp: dp-bridge@a000000 {
+ compatible = "ti,j721e-mhdp8546";
+
+ reg = <0x0 0xa000000 0x0 0x30a00>,
+ <0x0 0x4f40000 0x0 0x20>;
+ reg-names = "mhdptx", "j721e-intg";
+
+ clocks = <&k3_clks 217 11>;
+
+ interrupt-parent = <&gic500>;
+ interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;
+
+ power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
+
+ status = "disabled";
+
+ dp0_ports: ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+
dss: dss@4a00000 {
compatible = "ti,j721e-dss";
reg =
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 6/6] arm64: dts: ti: k3-j784s4-evm: Add DP0
2023-04-05 11:14 [PATCH 0/6] Add peripherals for J784S4 Jayesh Choudhary
` (4 preceding siblings ...)
2023-04-05 11:14 ` [PATCH 5/6] arm64: dts: ti: k3-j784s4-*: add DP & DP PHY Jayesh Choudhary
@ 2023-04-05 11:14 ` Jayesh Choudhary
5 siblings, 0 replies; 9+ messages in thread
From: Jayesh Choudhary @ 2023-04-05 11:14 UTC (permalink / raw)
To: nm, vigneshr
Cc: s-vadapalli, kristo, robh+dt, krzysztof.kozlowski+dt,
linux-arm-kernel, devicetree, linux-kernel, j-choudhary
From: Rahul T R <r-ravikumar@ti.com>
Add the endpoint nodes to describe connection from
DSS => MHDP => DisplayPort connector.
Also add the required nodes gpio expander 4 and pinmux
for main_i2c4 which is required for controlling DP Power
and set status of all the required nodes for DP0 as
okay
Signed-off-by: Rahul T R <r-ravikumar@ti.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
---
arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 77 ++++++++++++++++++++++++
1 file changed, 77 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
index 2b414fd973d0..03c9bf34cb1b 100644
--- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts
@@ -102,6 +102,28 @@ vdd_sd_dv: regulator-TLV71033 {
states = <1800000 0x0>,
<3300000 0x1>;
};
+
+ dp0_pwr_3v3: regulator-dp0-prw {
+ compatible = "regulator-fixed";
+ regulator-name = "dp0-pwr";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ gpio = <&exp4 0 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
+ dp0: dp0-connector {
+ compatible = "dp-connector";
+ label = "DP0";
+ type = "full-size";
+ dp-pwr-supply = <&dp0_pwr_3v3>;
+
+ port {
+ dp0_connector_in: endpoint {
+ remote-endpoint = <&dp0_out>;
+ };
+ };
+ };
};
&main_pmx0 {
@@ -169,6 +191,13 @@ dp0_pins_default: dp0-pins-default {
J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */
>;
};
+
+ main_i2c4_pins_default: main-i2c4-pins-default {
+ pinctrl-single,pins = <
+ J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */
+ J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */
+ >;
+ };
};
&wkup_pmx0 {
@@ -313,6 +342,7 @@ &serdes_refclk {
};
&dss {
+ status = "okay";
assigned-clocks = <&k3_clks 218 2>,
<&k3_clks 218 5>,
<&k3_clks 218 14>,
@@ -323,7 +353,12 @@ &dss {
<&k3_clks 218 22>;
};
+&serdes_wiz4 {
+ status = "okay";
+};
+
&serdes4 {
+ status = "okay";
serdes4_dp_link: phy@0 {
reg = <0>;
cdns,num-lanes = <4>;
@@ -335,8 +370,50 @@ serdes4_dp_link: phy@0 {
};
&mhdp {
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&dp0_pins_default>;
phys = <&serdes4_dp_link>;
phy-names = "dpphy";
};
+
+&dss_ports {
+ port {
+ dpi0_out: endpoint {
+ remote-endpoint = <&dp0_in>;
+ };
+ };
+};
+
+&main_i2c4 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&main_i2c4_pins_default>;
+ clock-frequency = <400000>;
+
+ exp4: gpio@20 {
+ compatible = "ti,tca6408";
+ reg = <0x20>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
+
+&dp0_ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ dp0_in: endpoint {
+ remote-endpoint = <&dpi0_out>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+ dp0_out: endpoint {
+ remote-endpoint = <&dp0_connector_in>;
+ };
+ };
+};
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread