* [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs
@ 2025-09-04 16:59 Prabhakar
2025-09-04 16:59 ` [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node Prabhakar
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Prabhakar @ 2025-09-04 16:59 UTC (permalink / raw)
To: Geert Uytterhoeven, Wolfram Sang, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Hi All,
This series adds I3C node to RZ/V2N and RZ/V2H(P) SoC DTSI files.
I3C was tested on RZ/V2H(P) and RZ/V2N EVKs using P3T1085UK Arduino
Shield Evaluation Board [0].
Disable I2C2 on PMOD connector CN6 and enable I3C.
Connect EVK TO P3T1085UK Arduino Shield Evaluation Board
P3T1085UK <-> EVK PMOD CN6
- J13[1] to CN6[3] (I3C_SCL)
- J13[2] to CN6[4] (I3C_SDA)
- J13[4] to CN6[5] (GND)
- J9[7] to CN6[11] (GND)
- J9[9] to CN6[6] (3.3V)
On P3T1085UK,
- JP2 pin1 to pin2 (I3C_SDA)
- JP3 pin1 to pin2 (I3C_SCL)
- JP1 pin2 to pin3 (VDD 3V3)
[0] https://www.nxp.com/design/design-center/development-boards-and-designs/analog-toolbox/arduino-shields-solutions/p3t1085uk-arduino-shield-evaluation-board:P3T1085UK-ARD
Test Logs:
--- RZ/V2H(P) ---
root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep i3c
i3c_0_pclk 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclk
i3c_0_pclkrw 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclkrw
i3c_0_tclk 1 2 0 200000000 0 0 50000 Y 12400000.i3c tclk
root@rzv2h-evk:~#
root@rzv2h-evk:~# cat /sys/class/hwmon/*/temp1_input
26687
26812
root@rzv2h-evk:~# cat /proc/interrupts | grep i3c
150: 38 0 0 0 GICv3 709 Edge i3c-resp
151: 2 0 0 0 GICv3 712 Edge i3c-rx
152: 0 0 0 0 GICv3 713 Edge i3c-tx
153: 0 0 0 0 GICv3 721 Level i3c-start
154: 0 0 0 0 GICv3 722 Level i3c-stop
155: 0 0 0 0 GICv3 724 Level i3c-tend
156: 0 0 0 0 GICv3 725 Level i3c-nack
root@rzv2h-evk:~# cat /sys/class/hwmon/*/temp1_input
26687
26812
root@rzv2h-evk:~# cat /proc/interrupts | grep i3c
150: 42 0 0 0 GICv3 709 Edge i3c-resp
151: 2 0 0 0 GICv3 712 Edge i3c-rx
152: 0 0 0 0 GICv3 713 Edge i3c-tx
153: 0 0 0 0 GICv3 721 Level i3c-start
154: 0 0 0 0 GICv3 722 Level i3c-stop
155: 0 0 0 0 GICv3 724 Level i3c-tend
156: 0 0 0 0 GICv3 725 Level i3c-nack
root@rzv2h-evk:~#
--- RZ/V2N ---
root@rzv2n-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep i3c
i3c_0_pclk 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclk
i3c_0_pclkrw 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclkrw
i3c_0_tclk 1 2 0 200000000 0 0 50000 Y 12400000.i3c tclk
root@rzv2n-evk:~# cat /proc/interrupts | grep i3c
65: 22 0 0 0 GICv3 709 Edge i3c-resp
66: 2 0 0 0 GICv3 712 Edge i3c-rx
67: 0 0 0 0 GICv3 713 Edge i3c-tx
68: 0 0 0 0 GICv3 721 Level i3c-start
69: 0 0 0 0 GICv3 722 Level i3c-stop
70: 0 0 0 0 GICv3 724 Level i3c-tend
71: 0 0 0 0 GICv3 725 Level i3c-nack
root@rzv2n-evk:~# cat /sys/class/hwmon/*/temp1_input
27000
27125
root@rzv2n-evk:~# cat /proc/interrupts | grep i3c
65: 26 0 0 0 GICv3 709 Edge i3c-resp
66: 2 0 0 0 GICv3 712 Edge i3c-rx
67: 0 0 0 0 GICv3 713 Edge i3c-tx
68: 0 0 0 0 GICv3 721 Level i3c-start
69: 0 0 0 0 GICv3 722 Level i3c-stop
70: 0 0 0 0 GICv3 724 Level i3c-tend
71: 0 0 0 0 GICv3 725 Level i3c-nack
root@rzv2n-evk:~#
Cheers,
Prabhakar
Lad Prabhakar (2):
arm64: dts: renesas: r9a09g057: Add I3C node
arm64: dts: renesas: r9a09g056: Add I3C node
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 33 ++++++++++++++++++++++
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 33 ++++++++++++++++++++++
2 files changed, 66 insertions(+)
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node
2025-09-04 16:59 [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Prabhakar
@ 2025-09-04 16:59 ` Prabhakar
2025-09-11 15:51 ` Geert Uytterhoeven
2025-09-04 16:59 ` [PATCH 2/2] arm64: dts: renesas: r9a09g056: " Prabhakar
2025-09-05 2:32 ` [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Rob Herring (Arm)
2 siblings, 1 reply; 6+ messages in thread
From: Prabhakar @ 2025-09-04 16:59 UTC (permalink / raw)
To: Geert Uytterhoeven, Wolfram Sang, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add I3C node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 806ce7901803..6eceb3018efd 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -607,6 +607,39 @@ scif: serial@11c01400 {
status = "disabled";
};
+ i3c: i3c@12400000 {
+ compatible = "renesas,r9a09g057-i3c", "renesas,r9a09g047-i3c";
+ reg = <0 0x12400000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>;
+ clock-names = "pclk", "tclk", "pclkrw";
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ierr", "terr", "abort", "resp",
+ "cmd", "ibi", "rx", "tx", "rcv",
+ "st", "sp", "tend", "nack",
+ "al", "tmo", "wu";
+ resets = <&cpg 0x96>, <&cpg 0x97>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
rspi0: spi@12800000 {
compatible = "renesas,r9a09g057-rspi";
reg = <0x0 0x12800000 0x0 0x400>;
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: renesas: r9a09g056: Add I3C node
2025-09-04 16:59 [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Prabhakar
2025-09-04 16:59 ` [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node Prabhakar
@ 2025-09-04 16:59 ` Prabhakar
2025-09-11 15:51 ` Geert Uytterhoeven
2025-09-05 2:32 ` [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Rob Herring (Arm)
2 siblings, 1 reply; 6+ messages in thread
From: Prabhakar @ 2025-09-04 16:59 UTC (permalink / raw)
To: Geert Uytterhoeven, Wolfram Sang, Magnus Damm, Rob Herring,
Krzysztof Kozlowski, Conor Dooley
Cc: linux-renesas-soc, devicetree, linux-kernel, Prabhakar, Biju Das,
Fabrizio Castro, Lad Prabhakar
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Add I3C node to RZ/V2N ("R9A09G056") SoC DTSI.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 33 ++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
index c1672eb490ca..2dd8f7fe5fff 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g056.dtsi
@@ -371,6 +371,39 @@ scif: serial@11c01400 {
status = "disabled";
};
+ i3c: i3c@12400000 {
+ compatible = "renesas,r9a09g056-i3c", "renesas,r9a09g047-i3c";
+ reg = <0 0x12400000 0 0x10000>;
+ clocks = <&cpg CPG_MOD 0x91>, <&cpg CPG_MOD 0x92>, <&cpg CPG_MOD 0x90>;
+ clock-names = "pclk", "tclk", "pclkrw";
+ interrupts = <GIC_SPI 674 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 676 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 677 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 678 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 679 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 680 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 681 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 682 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "ierr", "terr", "abort", "resp",
+ "cmd", "ibi", "rx", "tx", "rcv",
+ "st", "sp", "tend", "nack",
+ "al", "tmo", "wu";
+ resets = <&cpg 0x96>, <&cpg 0x97>;
+ reset-names = "presetn", "tresetn";
+ power-domains = <&cpg>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
i2c0: i2c@14400400 {
compatible = "renesas,riic-r9a09g056", "renesas,riic-r9a09g057";
reg = <0 0x14400400 0 0x400>;
--
2.51.0
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs
2025-09-04 16:59 [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Prabhakar
2025-09-04 16:59 ` [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node Prabhakar
2025-09-04 16:59 ` [PATCH 2/2] arm64: dts: renesas: r9a09g056: " Prabhakar
@ 2025-09-05 2:32 ` Rob Herring (Arm)
2 siblings, 0 replies; 6+ messages in thread
From: Rob Herring (Arm) @ 2025-09-05 2:32 UTC (permalink / raw)
To: Prabhakar
Cc: devicetree, Wolfram Sang, Geert Uytterhoeven, Fabrizio Castro,
Magnus Damm, Krzysztof Kozlowski, linux-renesas-soc,
Conor Dooley, Lad Prabhakar, Biju Das, linux-kernel
On Thu, 04 Sep 2025 17:59:07 +0100, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Hi All,
>
> This series adds I3C node to RZ/V2N and RZ/V2H(P) SoC DTSI files.
>
> I3C was tested on RZ/V2H(P) and RZ/V2N EVKs using P3T1085UK Arduino
> Shield Evaluation Board [0].
>
> Disable I2C2 on PMOD connector CN6 and enable I3C.
>
> Connect EVK TO P3T1085UK Arduino Shield Evaluation Board
> P3T1085UK <-> EVK PMOD CN6
> - J13[1] to CN6[3] (I3C_SCL)
> - J13[2] to CN6[4] (I3C_SDA)
> - J13[4] to CN6[5] (GND)
> - J9[7] to CN6[11] (GND)
> - J9[9] to CN6[6] (3.3V)
>
> On P3T1085UK,
> - JP2 pin1 to pin2 (I3C_SDA)
> - JP3 pin1 to pin2 (I3C_SCL)
> - JP1 pin2 to pin3 (VDD 3V3)
>
>
> [0] https://www.nxp.com/design/design-center/development-boards-and-designs/analog-toolbox/arduino-shields-solutions/p3t1085uk-arduino-shield-evaluation-board:P3T1085UK-ARD
>
> Test Logs:
> --- RZ/V2H(P) ---
> root@rzv2h-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep i3c
> i3c_0_pclk 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclk
> i3c_0_pclkrw 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclkrw
> i3c_0_tclk 1 2 0 200000000 0 0 50000 Y 12400000.i3c tclk
> root@rzv2h-evk:~#
> root@rzv2h-evk:~# cat /sys/class/hwmon/*/temp1_input
> 26687
> 26812
> root@rzv2h-evk:~# cat /proc/interrupts | grep i3c
> 150: 38 0 0 0 GICv3 709 Edge i3c-resp
> 151: 2 0 0 0 GICv3 712 Edge i3c-rx
> 152: 0 0 0 0 GICv3 713 Edge i3c-tx
> 153: 0 0 0 0 GICv3 721 Level i3c-start
> 154: 0 0 0 0 GICv3 722 Level i3c-stop
> 155: 0 0 0 0 GICv3 724 Level i3c-tend
> 156: 0 0 0 0 GICv3 725 Level i3c-nack
> root@rzv2h-evk:~# cat /sys/class/hwmon/*/temp1_input
> 26687
> 26812
> root@rzv2h-evk:~# cat /proc/interrupts | grep i3c
> 150: 42 0 0 0 GICv3 709 Edge i3c-resp
> 151: 2 0 0 0 GICv3 712 Edge i3c-rx
> 152: 0 0 0 0 GICv3 713 Edge i3c-tx
> 153: 0 0 0 0 GICv3 721 Level i3c-start
> 154: 0 0 0 0 GICv3 722 Level i3c-stop
> 155: 0 0 0 0 GICv3 724 Level i3c-tend
> 156: 0 0 0 0 GICv3 725 Level i3c-nack
> root@rzv2h-evk:~#
>
> --- RZ/V2N ---
> root@rzv2n-evk:~# cat /sys/kernel/debug/clk/clk_summary | grep i3c
> i3c_0_pclk 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclk
> i3c_0_pclkrw 1 2 0 100000000 0 0 50000 Y 12400000.i3c pclkrw
> i3c_0_tclk 1 2 0 200000000 0 0 50000 Y 12400000.i3c tclk
> root@rzv2n-evk:~# cat /proc/interrupts | grep i3c
> 65: 22 0 0 0 GICv3 709 Edge i3c-resp
> 66: 2 0 0 0 GICv3 712 Edge i3c-rx
> 67: 0 0 0 0 GICv3 713 Edge i3c-tx
> 68: 0 0 0 0 GICv3 721 Level i3c-start
> 69: 0 0 0 0 GICv3 722 Level i3c-stop
> 70: 0 0 0 0 GICv3 724 Level i3c-tend
> 71: 0 0 0 0 GICv3 725 Level i3c-nack
> root@rzv2n-evk:~# cat /sys/class/hwmon/*/temp1_input
> 27000
> 27125
> root@rzv2n-evk:~# cat /proc/interrupts | grep i3c
> 65: 26 0 0 0 GICv3 709 Edge i3c-resp
> 66: 2 0 0 0 GICv3 712 Edge i3c-rx
> 67: 0 0 0 0 GICv3 713 Edge i3c-tx
> 68: 0 0 0 0 GICv3 721 Level i3c-start
> 69: 0 0 0 0 GICv3 722 Level i3c-stop
> 70: 0 0 0 0 GICv3 724 Level i3c-tend
> 71: 0 0 0 0 GICv3 725 Level i3c-nack
> root@rzv2n-evk:~#
>
> Cheers,
> Prabhakar
>
> Lad Prabhakar (2):
> arm64: dts: renesas: r9a09g057: Add I3C node
> arm64: dts: renesas: r9a09g056: Add I3C node
>
> arch/arm64/boot/dts/renesas/r9a09g056.dtsi | 33 ++++++++++++++++++++++
> arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 33 ++++++++++++++++++++++
> 2 files changed, 66 insertions(+)
>
> --
> 2.51.0
>
>
>
My bot found new DTB warnings on the .dts files added or changed in this
series.
Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings
are fixed by another series. Ultimately, it is up to the platform
maintainer whether these warnings are acceptable or not. No need to reply
unless the platform maintainer has comments.
If you already ran DT checks and didn't see these error(s), then
make sure dt-schema is up to date:
pip3 install dtschema --upgrade
This patch series was applied (using b4) to base:
Base: attempting to guess base-commit...
Base: failed to guess base
If this is not the correct base, please add 'base-commit' tag
(or use b4 which does this automatically)
New warnings running 'make CHECK_DTBS=y for arch/arm64/boot/dts/renesas/' for 20250904165909.281131-1-prabhakar.mahadev-lad.rj@bp.renesas.com:
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: i3c@12400000 (renesas,r9a09g056-i3c): compatible:0: 'renesas,r9a09g056-i3c' is not one of ['renesas,r9a08g045-i3c', 'renesas,r9a09g047-i3c']
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
arch/arm64/boot/dts/renesas/r9a09g056n48-rzv2n-evk.dtb: i3c@12400000 (renesas,r9a09g056-i3c): compatible: ['renesas,r9a09g056-i3c', 'renesas,r9a09g047-i3c'] is too long
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dtb: i3c@12400000 (renesas,r9a09g057-i3c): compatible:0: 'renesas,r9a09g057-i3c' is not one of ['renesas,r9a08g045-i3c', 'renesas,r9a09g047-i3c']
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h48-kakip.dtb: i3c@12400000 (renesas,r9a09g057-i3c): compatible: ['renesas,r9a09g057-i3c', 'renesas,r9a09g047-i3c'] is too long
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: i3c@12400000 (renesas,r9a09g057-i3c): compatible:0: 'renesas,r9a09g057-i3c' is not one of ['renesas,r9a08g045-i3c', 'renesas,r9a09g047-i3c']
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dtb: i3c@12400000 (renesas,r9a09g057-i3c): compatible: ['renesas,r9a09g057-i3c', 'renesas,r9a09g047-i3c'] is too long
from schema $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node
2025-09-04 16:59 ` [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node Prabhakar
@ 2025-09-11 15:51 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2025-09-11 15:51 UTC (permalink / raw)
To: Prabhakar
Cc: Wolfram Sang, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-renesas-soc, devicetree, linux-kernel,
Biju Das, Fabrizio Castro, Lad Prabhakar
On Thu, 4 Sept 2025 at 18:59, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add I3C node to RZ/V2H(P) ("R9A09G057") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: renesas: r9a09g056: Add I3C node
2025-09-04 16:59 ` [PATCH 2/2] arm64: dts: renesas: r9a09g056: " Prabhakar
@ 2025-09-11 15:51 ` Geert Uytterhoeven
0 siblings, 0 replies; 6+ messages in thread
From: Geert Uytterhoeven @ 2025-09-11 15:51 UTC (permalink / raw)
To: Prabhakar
Cc: Wolfram Sang, Magnus Damm, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, linux-renesas-soc, devicetree, linux-kernel,
Biju Das, Fabrizio Castro, Lad Prabhakar
On Thu, 4 Sept 2025 at 18:59, Prabhakar <prabhakar.csengg@gmail.com> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add I3C node to RZ/V2N ("R9A09G056") SoC DTSI.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v6.18.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-09-11 15:51 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2025-09-04 16:59 [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Prabhakar
2025-09-04 16:59 ` [PATCH 1/2] arm64: dts: renesas: r9a09g057: Add I3C node Prabhakar
2025-09-11 15:51 ` Geert Uytterhoeven
2025-09-04 16:59 ` [PATCH 2/2] arm64: dts: renesas: r9a09g056: " Prabhakar
2025-09-11 15:51 ` Geert Uytterhoeven
2025-09-05 2:32 ` [PATCH 0/2] Add I3C support to RZ/V2N and RZ/V2H(P) SoCs Rob Herring (Arm)
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