[PATCH 0/3] Fixes for SM7150 dispcc driver

[PATCH 0/3] Fixes for SM7150 dispcc driver

[Jens Reidel]

The MDSS needs a reference to the MDSS_CORE reset since 6.17-rc,
otherwise video mode panel initialization appears to be broken.

Also ensure that the parent of dispcc_mdss_pclk0_clk_src gets prepared
and enabled to fix an "rcg didn't update its configuration" warning that
started occurring recently.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
Jens Reidel (3):
      dt-bindings: clock: sm7150-dispcc: Add MDSS_CORE reset
      clk: qcom: dispcc-sm7150: Add MDSS_CORE reset
      clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src

 drivers/clk/qcom/dispcc-sm7150.c               | 9 ++++++++-
 include/dt-bindings/clock/qcom,sm7150-dispcc.h | 3 +++
 2 files changed, 11 insertions(+), 1 deletion(-)
---
base-commit: 8f7f8b1b3f4c613dd886f53f768f82816b41eaa3
change-id: 20250919-sm7150-dispcc-fixes-31578cae5c1a

Best regards,
-- 
Jens Reidel <adrian@mainlining.org>

[PATCH 1/3] dt-bindings: clock: sm7150-dispcc: Add MDSS_CORE reset

[Jens Reidel]

Add the index for a reset inside the dispcc on SM7150 SoC.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
 include/dt-bindings/clock/qcom,sm7150-dispcc.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/qcom,sm7150-dispcc.h b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
index fc1fefe8fd7248bb160816cebb8cc4c51615a8dc..1e4e6432d5065b1dd3daed5b382732c9c9c09444 100644
--- a/include/dt-bindings/clock/qcom,sm7150-dispcc.h
+++ b/include/dt-bindings/clock/qcom,sm7150-dispcc.h
@@ -53,6 +53,9 @@
 #define DISPCC_SLEEP_CLK			41
 #define DISPCC_SLEEP_CLK_SRC			42
 
+/* DISPCC resets */
+#define DISPCC_MDSS_CORE_BCR			0
+
 /* DISPCC GDSCR */
 #define MDSS_GDSC				0
 

-- 
2.51.0

[PATCH 2/3] clk: qcom: dispcc-sm7150: Add MDSS_CORE reset

[Jens Reidel]

Add the offsets for a reset inside the dispcc on SM7150 SoC.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
 drivers/clk/qcom/dispcc-sm7150.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
index bdfff246ed3fe08dea3647da9582e166cfbb96f4..0a7f6ec7a2a737c6f6f0484c71dd80f3dbf758b6 100644
--- a/drivers/clk/qcom/dispcc-sm7150.c
+++ b/drivers/clk/qcom/dispcc-sm7150.c
@@ -20,6 +20,7 @@
 #include "clk-regmap-divider.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
 	DT_BI_TCXO,
@@ -951,6 +952,10 @@ static struct gdsc *dispcc_sm7150_gdscs[] = {
 	[MDSS_GDSC] = &mdss_gdsc,
 };
 
+static const struct qcom_reset_map dispcc_sm7150_resets[] = {
+	[DISPCC_MDSS_CORE_BCR] = { 0x2000 },
+};
+
 static const struct regmap_config dispcc_sm7150_regmap_config = {
 	.reg_bits	= 32,
 	.reg_stride	= 4,
@@ -965,6 +970,8 @@ static const struct qcom_cc_desc dispcc_sm7150_desc = {
 	.num_clks = ARRAY_SIZE(dispcc_sm7150_clocks),
 	.gdscs = dispcc_sm7150_gdscs,
 	.num_gdscs = ARRAY_SIZE(dispcc_sm7150_gdscs),
+	.resets = dispcc_sm7150_resets,
+	.num_resets = ARRAY_SIZE(dispcc_sm7150_resets),
 };
 
 static const struct of_device_id dispcc_sm7150_match_table[] = {

-- 
2.51.0

[PATCH 3/3] clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src

[Jens Reidel]

Set CLK_OPS_PARENT_ENABLE to ensure the parent gets prepared and enabled
when switching to it, fixing an "rcg didn't update its configuration"
warning.

Signed-off-by: Jens Reidel <adrian@mainlining.org>
---
 drivers/clk/qcom/dispcc-sm7150.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
index 0a7f6ec7a2a737c6f6f0484c71dd80f3dbf758b6..811d380a8e9f9bd8a8f1aecba567ebffdb893f5d 100644
--- a/drivers/clk/qcom/dispcc-sm7150.c
+++ b/drivers/clk/qcom/dispcc-sm7150.c
@@ -357,7 +357,7 @@ static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = {
 		.name = "dispcc_mdss_pclk0_clk_src",
 		.parent_data = dispcc_parent_data_4,
 		.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
-		.flags = CLK_SET_RATE_PARENT,
+		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
 		.ops = &clk_pixel_ops,
 	},
 };

-- 
2.51.0

Re: [PATCH 3/3] clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src

[Dmitry Baryshkov]

On Fri, Sep 19, 2025 at 02:34:32PM +0200, Jens Reidel wrote:
> Set CLK_OPS_PARENT_ENABLE to ensure the parent gets prepared and enabled
> when switching to it, fixing an "rcg didn't update its configuration"
> warning.
> 
> Signed-off-by: Jens Reidel <adrian@mainlining.org>
> ---
>  drivers/clk/qcom/dispcc-sm7150.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 2/3] clk: qcom: dispcc-sm7150: Add MDSS_CORE reset

[Dmitry Baryshkov]

On Fri, Sep 19, 2025 at 02:34:31PM +0200, Jens Reidel wrote:
> Add the offsets for a reset inside the dispcc on SM7150 SoC.
> 
> Signed-off-by: Jens Reidel <adrian@mainlining.org>
> ---
>  drivers/clk/qcom/dispcc-sm7150.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>


-- 
With best wishes
Dmitry

Re: [PATCH 1/3] dt-bindings: clock: sm7150-dispcc: Add MDSS_CORE reset

[Rob Herring (Arm)]

On Fri, 19 Sep 2025 14:34:30 +0200, Jens Reidel wrote:
> Add the index for a reset inside the dispcc on SM7150 SoC.
> 
> Signed-off-by: Jens Reidel <adrian@mainlining.org>
> ---
>  include/dt-bindings/clock/qcom,sm7150-dispcc.h | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: (subset) [PATCH 0/3] Fixes for SM7150 dispcc driver

[Bjorn Andersson]

On Fri, 19 Sep 2025 14:34:29 +0200, Jens Reidel wrote:
> The MDSS needs a reference to the MDSS_CORE reset since 6.17-rc,
> otherwise video mode panel initialization appears to be broken.
> 
> Also ensure that the parent of dispcc_mdss_pclk0_clk_src gets prepared
> and enabled to fix an "rcg didn't update its configuration" warning that
> started occurring recently.
> 
> [...]

Applied, thanks!

[2/3] clk: qcom: dispcc-sm7150: Add MDSS_CORE reset
      commit: 176465fd8c4e2cbb4410b5a66f6ba74ed491d2a5
[3/3] clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src
      commit: e3c13e0caa8ceb7dec1a7c4fcfd9dbef56a69fbe

Best regards,
-- 
Bjorn Andersson <andersson@kernel.org>

Re: [PATCH 3/3] clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src

[David Heidelberg]

On 19/09/2025 14:34, Jens Reidel wrote:
> Set CLK_OPS_PARENT_ENABLE to ensure the parent gets prepared and enabled
> when switching to it, fixing an "rcg didn't update its configuration"
> warning.
> 
> Signed-off-by: Jens Reidel <adrian@mainlining.org>
> ---
>   drivers/clk/qcom/dispcc-sm7150.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
> index 0a7f6ec7a2a737c6f6f0484c71dd80f3dbf758b6..811d380a8e9f9bd8a8f1aecba567ebffdb893f5d 100644
> --- a/drivers/clk/qcom/dispcc-sm7150.c
> +++ b/drivers/clk/qcom/dispcc-sm7150.c
> @@ -357,7 +357,7 @@ static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = {
>   		.name = "dispcc_mdss_pclk0_clk_src",
>   		.parent_data = dispcc_parent_data_4,
>   		.num_parents = ARRAY_SIZE(dispcc_parent_data_4),
> -		.flags = CLK_SET_RATE_PARENT,
> +		.flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
>   		.ops = &clk_pixel_ops,
>   	},
>   };
> 

Hello Jens,

do you know if in the addition to dispcc_mdss_pclk0_clk_src 
pclk1_clk_src may need  this flag too?

We sent similar patch for sdm845 with both receiving 
CLK_OPS_PARENT_ENABLE, as some sdm845/sm7150 device may have two DSI.

What do you think?

David

P.S. Added +Petr and +Konrad to Cc.

Re: [PATCH 3/3] clk: qcom: dispcc-sm7150: Fix dispcc_mdss_pclk0_clk_src

[Konrad Dybcio]

On 1/7/26 12:50 PM, David Heidelberg wrote:
> On 19/09/2025 14:34, Jens Reidel wrote:
>> Set CLK_OPS_PARENT_ENABLE to ensure the parent gets prepared and enabled
>> when switching to it, fixing an "rcg didn't update its configuration"
>> warning.
>>
>> Signed-off-by: Jens Reidel <adrian@mainlining.org>
>> ---
>>   drivers/clk/qcom/dispcc-sm7150.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/clk/qcom/dispcc-sm7150.c b/drivers/clk/qcom/dispcc-sm7150.c
>> index 0a7f6ec7a2a737c6f6f0484c71dd80f3dbf758b6..811d380a8e9f9bd8a8f1aecba567ebffdb893f5d 100644
>> --- a/drivers/clk/qcom/dispcc-sm7150.c
>> +++ b/drivers/clk/qcom/dispcc-sm7150.c
>> @@ -357,7 +357,7 @@ static struct clk_rcg2 dispcc_mdss_pclk0_clk_src = {
>>           .name = "dispcc_mdss_pclk0_clk_src",
>>           .parent_data = dispcc_parent_data_4,
>>           .num_parents = ARRAY_SIZE(dispcc_parent_data_4),
>> -        .flags = CLK_SET_RATE_PARENT,
>> +        .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
>>           .ops = &clk_pixel_ops,
>>       },
>>   };
>>
> 
> Hello Jens,
> 
> do you know if in the addition to dispcc_mdss_pclk0_clk_src pclk1_clk_src may need  this flag too?

Yes

Konrad