From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
To: chester62515@gmail.com, mbrugger@suse.com,
ghennadi.procopciuc@oss.nxp.com, s32@nxp.com,
bhelgaas@google.com, jingoohan1@gmail.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, Ionut.Vicovan@nxp.com,
larisa.grigore@nxp.com, Ghennadi.Procopciuc@nxp.com,
ciprianmarian.costea@nxp.com, bogdan.hamciuc@nxp.com,
Frank.li@nxp.com, linux-arm-kernel@lists.infradead.org,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, imx@lists.linux.dev,
Vincent Guittot <vincent.guittot@linaro.org>
Cc: cassel@kernel.org
Subject: Re: [PATCH 0/4 v6] PCI: s32g: Add support for PCIe controller
Date: Tue, 25 Nov 2025 11:06:26 +0530 [thread overview]
Message-ID: <176404898659.18373.12076537585341452677.b4-ty@kernel.org> (raw)
In-Reply-To: <20251121164920.2008569-1-vincent.guittot@linaro.org>
On Fri, 21 Nov 2025 17:49:16 +0100, Vincent Guittot wrote:
> The S32G SoC family has 2 PCIe controllers based on Designware IP.
>
> Add the support for Host mode.
>
> Change since v5:
>
> - Removed relocatable bit in yaml
> - Dropped pcie-nxp-s32g-regs.h and moved reg definition in pcie-nxp-s32g.c
> - Removed a useless ret
> - Change kconfig from tri to bool because of memblock_start_of_DRAM()
>
> [...]
Applied, thanks!
[1/4] dt-bindings: PCI: s32g: Add NXP PCIe controller
commit: dd17ec3df57b7bd0d23f3a17124d59b2740d81e4
[2/4] PCI: dw: Add more registers and bitfield definition
commit: bd1be33651b21ce15eee8fa2f080109e3eaa8e29
[3/4] PCI: s32g: Add initial PCIe support (RC)
commit: c403d6d7282b72fe1a0812c99beeeefb1a7e1f4b
[4/4] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver
commit: 58fc675c34c583771d412aa89fb364c750fadacf
Best regards,
--
Manivannan Sadhasivam <mani@kernel.org>
prev parent reply other threads:[~2025-11-25 5:36 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-21 16:49 Vincent Guittot
2025-11-21 16:49 ` [PATCH 1/4 v6] dt-bindings: PCI: s32g: Add NXP " Vincent Guittot
2025-11-21 16:49 ` [PATCH 2/4 v6] PCI: dw: Add more registers and bitfield definition Vincent Guittot
2025-11-21 16:49 ` [PATCH 3/4 v6] PCI: s32g: Add initial PCIe support (RC) Vincent Guittot
2025-11-21 16:49 ` [PATCH 4/4 v6] MAINTAINERS: Add MAINTAINER for NXP S32G PCIe driver Vincent Guittot
2025-11-25 19:21 ` Bjorn Helgaas
2025-11-25 20:16 ` Frank Li
2025-11-26 21:41 ` Bjorn Helgaas
2025-11-26 21:47 ` Ciprian Marian Costea
2025-11-26 22:04 ` Bjorn Helgaas
2025-11-27 6:53 ` Vincent Guittot
2025-11-25 5:36 ` Manivannan Sadhasivam [this message]
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